Connexion
Optical connectivity – and especially silicon photonics – is expected to become a crucial technology to enable connectivity for next-generation datacenters, particularly those designed HPC applications. With ever-increasing bandwidth requirements needed to keep up with (and keep scaling out) system performance, copper signaling alone won't be enough to keep up. To that end, several companies are developing silicon photonics solutions, including fab providers like TSMC, who this week outlined its 3D Optical Engine roadmap as part of its 2024 North American Technology Symposium, laying out its plan to bring up to 12.8 Tbps optical connectivity to TSMC-fabbed processors.
TSMC's Compact Universal Photonic Engine (COUPE) stacks an electronics integrated circuit on photonic integrated circuit (EIC-on-PIC) using the company's SoIC-X packaging technology. The foundry says that usage of its SoIC-X enables the lowest impedance at the die-to-die interface and therefore the highest energy efficiency. The EIC itself is produced at a 65nm-class process technology.
TSMC's 1st Generation 3D Optical Engine (or COUPE) will be integrated into an OSFP pluggable device running at 1.6 Tbps. That's a transfer rate well ahead of current copper Ethernet standards – which top out at 800 Gbps – underscoring the immediate bandwidth advantage of optical interconnects for heavily-networked compute clusters, never mind the expected power savings.
Looking further ahead, the 2nd Generation of COUPE is designed to integrate into CoWoS packaging as co-packaged optics with a switch, allowing optical interconnections to be brought to the motherboard level. This version COUPE will support data transfer rates of up to 6.40 Tbps with reduced latency compared to the first version.
TSMC's third iteration of COUPE – COUPE running on a CoWoS interposer – is projected to improve on things one step further, increasing transfer rates to 12.8 Tbps while bringing optical connectivity even closer to the processor itself. At present, COUPE-on-CoWoS is in the pathfinding stage of development and TSMC does not have a target date set.
Ultimately, unlike many of its industry peers, TSMC has not participated in the silicon photonics market up until now, leaving this to players like GlobalFoundries. But with its 3D Optical Engine Strategy, the company will enter this important market as it looks to make up for lost time.
TSMC has been offering its System-on-Wafer integration technology, InFO-SoW, since 2020. For now, only Cerebras and Tesla have developed wafer scale processor designs using it, as while they have fantastic performance and power efficiency, wafer-scale processors are extremely complex to develop and produce. But TSMC believes that not only will wafer-scale designs ramp up in usage, but that megatrends like AI and HPC will call for even more complex solutions: vertically stacked system-on-wafer designs.
Tesla Dojo's wafer-scale processors — the first solutions based based on TSMC's InFO-SoW technology that are in mass production — have a number of benefits over typical system-in-packages (SiPs), including low-latency high-bandwidth core-to-core communications, very high performance and bandwidth density, relatively low power delivery network impendance, high performance efficiency, and redunancy.
But with InFO-SoW and other wafer scale integration methods, processor designers have to rely solely on on-chip memory. This is perfectly adequate for many applications, but it may not be enough for next-generation AI workloads. Furthermore, with InFO-SoW, the whole wafer has to be processed using one fabrication technology, which may not be optimal, or too expensive for certain designs.
So, with its next-generation system-on-wafer platform, TSMC plans to bring together two of its packaging technologies: InFO-SoW and System on Integrated Chips (SoIC), which will allow it to stack memory or logic on top of a system-on-wafer using its Chip-on-Wafer (CoW) method. The CoW-SoW technology, which the company announced at its North American Technology Symposium, will be ready for mass production in 2027.
For now, TSMC is mostly talking about wedding wafer scale processors with HBM4 memory. And given that HBM4 stacks will feature a 2048-bit interface, its tighter integration with logic is something that the industry is considering.
"So, in the future, using wafer level integrations [will allow] our customers to integrate even more logic and memory together," said Kevin Zhang, Vice President of Business Development at TSMC. "SoW is no longer a fiction, this is something we already work with our customers [on] to produce some of the products already in place. This we think by leveraging our advanced wafer level integration technology, we can provide our customer a very important the path allow them to continue to grow their capability to bring in more computation, more energy efficient computation, to their AI cluster or [supercomputer]."
While the bulk of attention on TSMC is aimed at its leading-edge nodes, such as N3E and N2, loads of chips will continue to be made using more mature and proven process technologies for years to come. Which is why TSMC has continued to refine its existing nodes, including its current-generation 5nm-class offerings. To that end, at its North American Technology Symposium 2024, the company introduced a new, optimized 5nm-class node: N4C.
TSMC's N4C process belongs to the company's 5nm-class family of fab nodes and is a superset of N4P, the most advanced technology in that family. In a bid to further bring down 5nm manufacturing costs, for TSMC is implementing several changes for N4C, including rearchitecting their standard cell and SRAM cell, changing some design rules, and reducing the number of masking layers. As a result of these improvements, the company expects N4C to achieve both smaller die sizes as well as a reduction in production complexity, which in turn will bring die costs down by up to 8.5%. Furthermore, with the same wafer-level defect density rate as N4P, N4C stands to offer even higher functional yields thanks to its die area reduction.
"So, we are not done with our 5nm and 4nm [technologies]," said Kevin Zhang, Vice President of Business Development at TSMC. "From N5 to N4, we have achieved 4% density improvement optical shrink, and we continue to enhance the transistor performance. Now we bring in N4C to our 4 nm technology portfolio. N4C allows our customers to reduce their costs by remove some of the masks and to also improve on the original IP design like a standard cell and SRAM to further reduce the overall product level cost of ownership."
TSMC says that N4C can use the same design infrastructure as N4P, though it is unclear whether N5 and N4P IP can be re-used for N4C-based chips. Meanwhile, TSMC indicates that it offers various options for chipmakers to find the right balance between cost benefits and design effort, so companies interested in adopting a 4nm-class process technologies could well adopt N4C.
The development of N4C comes as many of TSMC's chip design customers are preparing to launch chips based on the company's final generation of FinFET process technology, the 3nm N3 series. While N3 is expected to be a successful family, the high costs of N3B have been an issue, and the generation is marked by diminishing performance and transistor density returns altogether. Consequently, N4C could well become a major, long-lived node at TSMC, serving as a good fit for customers who want to stick to a more cost-effective FinFET node.
"This is a very significant enhancement, we are working with our customer, basically to extract more value from their 4 nm investment," Zhang said.
TSMC expects to start volume production of N4C chips some time next year. And with TSMC having produced 5nm-class for nearly half a decade at that point, N4C should be able to hit the ground running in terms of volume and yields.
Taiwan Semiconductor Manufacturing Co. provided several important updates about its upcoming process technologies at its North American Technology Symposium 2024. At a high level, TSMC's 2 nm plans remain largely unchanged: the company is on track to start volume production of chips on it's first-generation GAAFET N2 node in the second half of 2025, and N2P will succeed N2 in late 2026 – albeit without the previously-announced backside power delivery capabilities. Meanwhile, the whole N2 family will be adding TSMC's new NanoFlex capability, which allows chip designers to mix and match cells from different libraries to optimize performance, power, and area (PPA).
One of the key announcements of the event is TSMC's NanoFlex technology, which will be a part of the company's complete N2 family of production nodes (2 nm-class, N2, N2P, N2X). NanoFlex will enable chip designers to mix and match cells from different libraries (high performance, low power, area efficient) within the same block design, allowing designers to fine tune their chip designs to improve performance or lower power consumption.
TSMC's contemporary N3 fabrication process already supports a similar capability called FinFlex, which also allows designers to use cells from different libraries. But since N2 relies on gate-all-around (GAAFET) nanosheet transistors, NanoFlex gives TSMC some additional controls: firstly, TSMC can optimize channel width for performance and power and then build short cells (for area and power efficiency) or tall cells (for up to 15% higher performance).
When it comes to timing, TSMC's N2 is set to enter risk production in 2025 and high-volume manufacturing (HVM) in the second half of 2025, so it looks like we are going to see N2 chips in retail devices in 2026. Compared to N3E, TSMC expects N2 to increase performance by 10% to 15% at the same power, or reduce power consumption by 25% to 30% at the same frequency and complexity. As for chip density, the foundry is looking at a 15% density increase, which is a good degree of scaling by contemporary standards.
N2 will be followed by performance-enhanced N2P, as well as the voltage-enhanced N2X in 2026. Although TSMC once said that N2P would add backside power delivery network (BSPDN) in 2026, it looks like this will not be the case and N2P will use regular power delivery circuitry. The reason for this is unclear, but it looks like the company decided not to add a costly feature to N2P, but to reserve it to its next-generation node, which will also be available to customers in late 2026.
N2 is still expected to feature a major innovation related to power: super-high-performance metal-insulator-metal (SHPMIM) capacitors, which are are being added to improve power supply stability. The SHPMIM capacitor offers more than twice the capacity density of TSMC's existing super-high-density metal-insulator-metal (SHDMIM) capacitor. Additionally, the new SHPMIM capacitor cuts sheet resistance (Rs in Ohm/square) and via resistance (Rc) by 50% compared to its predecessor.
With the arrival of spring comes showers, flowers, and in the technology industry, TSMC's annual technology symposium series. With customers spread all around the world, the Taiwanese pure play foundry has adopted an interesting strategy for updating its customers on its fab plans, holding a series of symposiums from Silicon Valley to Shanghai. Kicking off the series every year – and giving us our first real look at TSMC's updated foundry plans for the coming years – is the Santa Clara stop, where yesterday the company has detailed several new technologies, ranging from more advanced lithography processes to massive, wafer-scale chip packing options.
Today we're publishing several stories based on TSMC's different offerings, starting with TSMC's marquee announcement: their A16 process node. Meanwhile, for the rest of our symposium stories, please be sure to check out the related reading below, and check back for additional stories.
Headlining its Silicon Valley stop, TSMC announced its first 'angstrom-class' process technology: A16. Following a production schedule shift that has seen backside power delivery network technology (BSPDN) removed from TSMC's N2P node, the new 1.6nm-class production node will now be the first process to introduce BSPDN to TSMC's chipmaking repertoire. With the addition of backside power capabilities and other improvements, TSMC expects A16 to offer significantly improved performance and energy efficiency compared to TSMC's N2P fabrication process. It will be available to TSMC's clients starting H2 2026.
At a high level, TSMC's A16 process technology will rely on gate-all-around (GAAFET) nanosheet transistors and will feature a backside power rail, which will both improve power delivery and moderately increase transistor density. Compared to TSMC's N2P fabrication process, A16 is expected to offer a performance improvement of 8% to 10% at the same voltage and complexity, or a 15% to 20% reduction in power consumption at the same frequency and transistor count. TSMC is not listing detailed density parameters this far out, but the company says that chip density will increase by 1.07x to 1.10x – keeping in mind that transistor density heavily depends on the type and libraries of transistors used.
The key innovation of TSMC's A16 node, is its Super Power Rail (SPR) backside power delivery network, a first for TSMC. The contract chipmaker claims that A16's SPR is specifically tailored for high-performance computing products that feature both complex signal routes and dense power circuitry.
As noted earlier, with this week's announcement, A16 has now become the launch vehicle for backside power delivery at TSMC. The company was initially slated to offer BSPDN technology with N2P in 2026, but for reasons that aren't entirely clear, the tech has been punted from N2P and moved to A16. TSMC's official timing for N2P in 2023 was always a bit loose, so it's hard to say if this represents much of a practical delay for BSPDN at TSMC. But at the same time, it's important to underscore that A16 isn't just N2P renamed, but rather it will be a distinct technology from N2P.
TSMC is not the only fab pursuing backside power delivery, and accordingly, we're seeing multiple variations on the technique crop up at different fabs. The overall industry has three approaches for BSPDN: Imec's Buried Power Rail, Intel's PowerVia, and now TSMC's Super Power Rail.
The oldest technique, Imec's Buried Power Rail, essentially places power delivery network on the backside of the wafer and then connects power rail of logic cells to power contact using nano TSVs. This enables some area scaling and does not add too much complexity to production. The second implementation, Intel's PowerVia, connects power to the cell or transistor contact, which provides a better result, but at the cost of complexity.
Finally, we have TSMC's new Super Power Rail BSPDN technology, which connects a backside power network directly to each transistor's source and drain. According to TSMC, this is the most efficient technology in terms of area scaling, but the trade-off is that it's the most complex (and expensive) when it comes to production.
That TSMC has opted to go with the most complex version of BSPDN may be part of the reason that we've seen it removed from N2P, as implementing it will ultimately add to both time and costs. This leaves A16 as TSMC's premiere performance node for the 2026/2027 time-frame, while N2P can be positioned to offer a more balanced combination of performance and cost efficiency.
Finally, as with Intel, we're also seeing TSMC adopt a new process node naming convention starting with this generation of technology. The name itself is largely arbitrary – and this has already been the case in the fab industry for several years now – but with current node names already in the single digits (e.g. N2), the industry has needed to re-calibrate node names to something smaller than the nanometer. And thus we've arrived at the 'angstrom era.' But regardless of what exactly it's called or why it's called that, the important point is that A16 will be the next generation node beyond TSMC's 2nm-class products.
TSMC expects to start volume production on A16 in H2 2026, so it is likely that the first products based on this technology will hit the market in 2027. Given the timing, the production node will presumably compete against Intel's 14A; though at 2+ years out and with no one producing BSPDN in volume today, there's still a lot of time for plans and roadmaps to change.
Seagate Technology has reportedly notified its customers abouts its plans to raise prices on new hard drive orders and for demands that exceed prior agreements, echoing a similar move by Western Digital, which increased its prices earlier this month. These changes come in response to a surge in demand for high-capacity HDDs and constraints in supply due to decreased production capabilities of both Seagate and Western Digital, reports TrendForce.
According to industry insights reported by TechNews, the sector anticipates that the scarcity of high-capacity HDD products will persist throughout the current quarter and possibly extend over the entire year. It is forecasted that HDD prices will rise by 5% to 10% in Q2 2024 alone and could increase further as a reault of the ongoing challenges faced by the storage industry.
The primary driver behind Seagate's decision is increased demand for high-capacity HDDs, which are used to train AI models. This demand spike, coupled with a reduction in production output from hard drive makers, has created a significant supply-demand imbalance. As a result, Seagate has decided to adjust their pricing strategy to manage the situation. Further exacerbating the issue are global inflationary pressures which continue to inflate costs across the board, which also contributed to the company's decision to increase prices, Seagate said in a message to clients published by TrendForce.
Seagate emphasized that its reduced production capacity has been a major challenge, hindering the company's ability to fulfill customer demands fully and promptly.
"As a result, we will be implementing price increases effective immediately on new orders and for demand that is over and above previously committed volumes," the alleged memo from Seagate reads. "Supply constraints are expected to continue and as such we anticipate that prices will continue to increase in the coming quarters."
Earlier this month Western Digital also informed its customers about price hikes for its HDD and SSD products. This notification was based on similar issues — higher than anticipated demand across the whole product range and additional supply chain challenges affecting the electronics sector. Western Digital's announcement made it clear that these disruptions are likely to continue, prompting further price adjustments.
Sources: TrendForce, TrendForce, TechNews
As Qualcomm prepares for the mid-year launch of their forthcoming Snapdragon X SoCs for PCs, and the eagerly anticipated Oryon CPU cores within, the company is finally shoring up their official product plans, and releasing some additional technical details in the process. Thus far the company has been demonstrating their Snapdragon X Elite SoC in its highest-performing, fully-enabled configuration. But the retail Snapdragon X Elite will not be a single part; instead, Qualcomm is preparing a whole range of chip configurations for various price/performance tiers in the market. Altogether, there will be 3 Snapdragon X Elite SKUs that differ in CPU and GPU performance.
As well, the company is introducing a second Snapdragon X tier, Snapdragon X Plus, for those SKUs positioned below the Elite performance tier. As of today, this will be a single configuration. But if the Snapdragon X lineup is successful and demand warrants it, I would not be surprised to see Qualcomm expand it further – as they have certainly left themselves the room for it in their product stack. In the meantime, with Qualcomm’s expected launch competition now shipping (Intel Core Ultra Meteor Lake and AMD Ryzen Mobile 8040 Hawk Point), the company is also very confident that even these reduced performance Snapdragon X Plus chips will be able to beat Intel and AMD in multithreaded performance – never mind the top-tier Snapdragon X Elite chips.
Qualcomm will be launching this expanded four chip stack at once; so both Snapdragon X Elite and Snapdragon X Plus tier devices should be available at the same time. The company’s goal is still to have devices on the shelf “mid-year”, although the company isn’t providing any more precise guidance than that. With Qualcomm’s CEO, Cristiano Amon, set to deliver a Computex keynote in June, I expect we’ll get more specific details on timings then, along with the company and its partners using the event to announce and showcase some retail laptop designs. So this is very much looking like a summer launch at the moment.
In the meantime, Qualcomm is already showing off what their Snapdragon X Plus chips can do with a fresh set of live benchmarks, akin to their Snapdragon X Elite performance previews from October 2023. We’ll dive into those in a bit, but suffice it to say, Qualcomm knows the score, and they want to make sure the entire world knows when they’re winning.
As Seagate ramps up shipments of its new heat assisted magnetic recording (HAMR)-based Mozaic 3+ hard drive platform, the company is both in the enviable position of shipping the first major new hard drive technology in a decade, and the much less enviable position of proving the reliability of the first major new hard drive technology in a decade. Due to HAMR's use of temporal heating with its platters, as well as all-new read/write heads, HAMR introduces multiple new changes at once that have raise questions about how reliable the technology will be. Looking to address these matters (and further promote their HAMR drives), Seagate has published a fresh blog post outlining the company's R&D efforts, and why the company expects their HAMR drives to last several years – as long or longer than current PMR hard drives.
According to the company, the reliability of Mozaic 3+ drives on par with traditional drives relying on perpendicular magnetic recording (PMR), the company says. In fact, components of HAMR HDDs have demonstrated a 50% increase in reliability over the past two years. Seagate says that Mozaic 3+ drives boast impressive durability metrics: their read/write heads have demonstrated capacity to handle over 3.2 petabytes of data transfer over 6,000 hours of operation, which exceeds data transfers of typical nearline hard drives by 20 times. Accordingly, Seagate is rating these drives for a mean time between failure (MTBF) 2.5 million hours, which is in-line with PMR-based drives.
Based on their field stress tests, involving over 500,000 Mozaic 3+ drives, Seagate says that the heads of Mozaic 3+ drives will last over seven years, surpassing the typical lifespan of current PMR-based drives. Generally, customers anticipate that modern PMR drives will last between four and five years with average usage, so these drives would exceed current expectations.
Altogether, Seagate is continuing aim for a seamless transition from PMR to HAMR drives in customer systems. That means ensuring that these new drives can fit into existing data center infrastructures without requiring any changes to enterprise specifications, warranty conditions, or form factors.
Samsung Electronics has started mass production of its 9th generation of V-NAND memory. The first dies based on their latest NAND tech come in a 1 Tb capacity using a triple-level cell (TLC) architecture, with data transfer rates as high as 3.2 GT/s. The new 3D TLC NAND memory will initially be used to build high-capacity and high-performance SSDs, which will help to solidify Samsung's position in the storage market.
Diving right in, Samsung is conspicuously avoiding to list the number of layers in their latest generation NAND, which is the principle driving factor in increasing capacity generation-on-generation. The company's current 8th gen V-NAND is 236 layers – similar to its major competitors – and word on the street is that 9th gen V-NAND ups that to 290 layers, though this remains to be confirmed.
Regardless, Samsung says that its 9th generation V-NAND memory boasts an approximate 50% improvement in bit density over its 8th generation predecessor. Driving this gains, the company cites the miniaturization of the cell size, as well as the integration of enhanced memory cell technologies that reduce interference and extend the lifespan of the cells. With their latest NAND technology, Samsung has also been able to eliminate dummy channel holes, thus reducing the planar area of the memory cells.
Interestingly, today's announcement also marks the first time that Samsung has publicly confirmed their use of string stacking in their NAND, referring to it as their "double-stack structure." The company is widely believed to have been using sting stacking back in their 8th generation NAND as well, however this was never confirmed by the company. Regardless, the use of string stacking is only going to increase from here, as vendors look to keep adding layers to their NAND dies, while manufacturing variability and channel hole tolerances make it difficult to produce more than 150-200 layers in a single stack.
| Samsung TLC V- NAND Flash Memory | ||
| 9th Gen V-NAND | 8th Gen V-NAND | |
| Layers | 290? | 236 |
| Decks | 2 (x145) | 2 (x118) |
| Die Capacity | 1 Tbit | 1 Tbit |
| Die Size (mm2) | ?mm2 | ?mm2 |
| Density (Gbit/mm2) | ? | ? |
| I/O Speed | 3.2 GT/s (Toggle 5.1) |
2.4 GT/s (Toggle 5.0) |
| Planes | 6? | 4 |
| CuA / PuC | Yes | Yes |
Speaking of channel holes, another key technological enhancement in the 9th gen V-NAND is Samsung's advanced 'channel hole etching' technology. This process improves manufacturing productivity by enabling the simultaneous creation of electron pathways within a double-stack structure. This method is crucial as it enables efficient drilling through more layers, which is increasingly important as cell layers are added.
The latest V-NAND also features the introduction of a faster NAND flash interface, Toggle DDR 5.1, which boosts peak data transfer rates by 33% to 3.2 GT/s, or almost 400MB/sec for a single die. Additionally, 9th gen V-NAND's power consumption has been reduced by 10%, according to Samsung. Though Samsung doesn't state under what conditions – presumably, this is at iso-frequency rather than max frequency.
Samsung's launch of 1Tb TLC V-NAND is set to be followed by the release of a quad-level cell (QLC) model later this year.
"We are excited to deliver the industry’s first 9th-gen V-NAND which will bring future applications leaps forward," said SungHoi Hur, Head of Flash Product & Technology of the Memory Business at Samsung Electronics. "In order to address the evolving needs for NAND flash solutions, Samsung has pushed the boundaries in cell architecture and operational scheme for our next-generation product. Through our latest V-NAND, Samsung will continue to set the trend for the high-performance, high-density solid-state drive (SSD) market that meets the needs for the coming AI generation."
Lexar has a long history of serving the flash-based consumer storage market in the form of SSDs, memory cards, and USB flash drives. After having started out as a Micron brand, the company was acquired by Longsys which has diversified its product lineup with regular introduction of new products. Recently, the company announced a number of portable SSDs targeting different market segments. The Lexar SL500 Portable SSD is one of the moderately priced 20 Gbps PSSDs in that set.
The SL500 is able to achieve its price point thanks to the use of a native USB flash controller - the Silicon Motion SM2320. The unique aspect is the use of YMTC 3D TLC NAND (compared to the usual Micron or BiCS NAND that we have seen in previous SM2320-based PSSDs). Read on for a detailed look at the SL500, including an analysis of its internals and evaluation of its performance consistency, power consumption, and thermal profile.
While desktop PC power supplies receive the bulk of enthusiasts’ attention for good reasons – not the least of which being the vast selection of options that comes from being a standardized part – power supplies as a whole aren’t just a concern for big PCs. With the majority of PC sales having flipped to notebook sales some years ago, notebook power supplies already lead the market in volume. And while most laptops don’t need the kind of massively powered PSUs that dominate the desktop space, even that is slowly changing as desktop replacement-class laptops increasingly grow in performance and power consumption.
Perhaps the poster-child for the high-performance, high-powered laptop is Eurocom, who has a long history of developing heavy-duty DTR laptops that are all but portable desktop systems. Following recent trends in GPU power consumption and in GPU popularity for both gaming and AI workloads, the company has been selling a range of “mobile supercomputers”, which are practically large, tailor-made laptops that rival even the best of desktop computers – and have the power requirements to match.
In order to power their own high-end laptops, Eurocom has developed a rather unusual 780W AC adapter for high-performance laptops. Intended to power the most powerful of powerful laptops, their latest power adapter can supply over three-quarters of a kilowatt of DC power; a desktop-like wattage for a desktop-like device. It’s a laptop power adapter that’s unique in its scale, and with some room to scale up even further.
| Eurocom 780W AC Adapter Power specifications |
|
| RAIL | +20V |
| MAX OUTPUT | 39A |
| 780W | |
| DIMENSIONS | 325 x 110 x 40mm, 1.38kg |
| AC INPUT | 90 - 264 VAC, 50 - 60 Hz |
| MSRP | PSU: $299, Cable: $129+ |
Eurocom has offered this adapter for a few years now. But it’s taken on a new life as more laptops have been released that use such a large adapter (or two smaller 300W-ish power adapters). And, critically, Eurocom has made additional DC cable/connector sets for other manufactuers’ laptops, significantly increasing the number of systems it’s compatible with. Currently, Eurocom offers DC cables for the following laptops:
Externally, the Eurocom 780W AC adapter looks like a hybrid between a PC PSU and a laptop adapter. It is shaped like an oversized laptop AC adapter but has a metallic body and cooling vents/fans. Eurocom advertises that it weighs “only 1.34kg”, which is the weight of an entire 14-inch laptop by comparison, but is relatively lightweight for a PSU with that kind of power output. The company logo is debossed across the top side of the adapter, with four round anti-slip pads found at its bottom. Care needs to be taken while moving it around because the metallic edges and weight can spell trouble for wooden surfaces.
Eurocom installed a small information display on the AC adapter, which shows the current, voltage, and power output, as well as the temperature of the adapter. It is not perfectly accurate – we can see it was reading a 12W load without a DC cable attached to the adapter – but it works as a basic reference. Next to it, there is a heavy-duty metallic connector for the DC cable. On the other side we can find a typical three-prong C14 AC cable receptacle, as well as an on/off switch, which is not something commonly found on laptop AC adapters.
Opening up the chassis, we can see that the Eurocom 780W AC adapter is not unlike common PC PSUs – just less complex due to the need to only generate a single 20V rail. The basic layout is identical, with an AC filter at the input consisting of four Y capacitors, two X capacitors, and two substantial filtering inductors, that leads to a rectifying bridge. The GBJ1508 bridge is made by HY Electronic Cayman Ltd, a Taiwanese company we're encountering for the first time.
Then we have an APFC circuitry with a massive Aishi 450V/560μF capacitor and a large filtering coil being its passive components, with a Toshiba K31N60W regulator on the same heatsink as the two MOSFETs that form a typical half-bridge configuration. Following that we have a small transformer and two Infineon 045N10N MOSFETs to generate the 20V power output. Cooling is provided by two Protechnic Electric MGT3812XB-W20 38 mm fans, which are small but high quality products with a double-ball bearing engine.
For the testing of PSUs, we are using high precision electronic loads with a maximum power draw of 2700 Watts, a Rigol DS5042M 40 MHz oscilloscope, an Extech 380803 power analyzer, two high precision UNI-T UT-325 digital thermometers, an Extech HD600 SPL meter, and various other bits and parts.
The average efficiency of the Eurocom 780W AC adapter is very high, at 91.6% when the PSU is powered from an 230V AC source and drops down to 90.9% when powered from an 115V AC source. There is no 80Plus or similar efficiency certification covering this PSU, but there is legislation such as the Ecodesign 2019/1782 directive, and, even though the manufacturer does not fully publish its performance specs as the directive requires, the Eurocom 780W adapter seems to easily meet them. We must mention that this kind of PSU has an advantage over classic PC PSUs because it only generates a single voltage line, and conversion losses are lower, so it should not be directly compared to any multi-voltage output PSU.
The two small fans of the Eurocom 780W AC adapter seem hardwired to the power output of the unit, largely ignoring the temperature of the adapter and adjusting their speed only according to the load. Up to 40% load, which should cover the power needs of most gaming laptops anyway, the adapter is practically entirely silent. The speed of the fan gradually increases when the load is greater than 330 Watts, reaching terrifying noise figures at maximum load. Given the nature of the adapter, it is highly unlikely that it will operate at such high a load for prolonged periods of time, as even the laptops that require 2x330 Watt adapters will not continuously sustain such a high load.
The electrical performance of the Eurocom 780W AC adapter is surprisingly good compared to its datasheet specifications. Eurocom claims a maximum voltage ripple of 200 mV but we recorded a maximum of 116 mV, which is alright for a 20 V rail and better than we expected due to the mediocre secondary side filtering. Voltage regulation is very good, at just 1.2% across the nominal load range.
| Main Output | ||||||||
| Load (Watts) | 158.03 | 394.68 | 586.46 | 780.78 | ||||
| Load (Percent) | 20% Load | 50% Load | 75% Load | 100% Load | ||||
| Amperes | Volts | Amperes | Volts | Amperes | Volts | Amperes | Volts | |
| 20 V | 7.8 | 20.26 | 19.5 | 20.24 | 29.25 | 20.05 | 39 | 20.02 |
| Line | Regulation (20% to 100% load) |
Voltage Ripple (mV) | |||||
| 20% Load | 50% Load | 75% Load | 100% Load | ||||
| 20V | 1.2% | 44 | 66 | 82 | 116 | ||
During our routine evaluation, we examine the fundamental protection features of all power supply units we review, including Over Current Protection (OCP), Over Voltage Protection (OVP), Over Power Protection (OPP), and Short Circuit Protection (SCP). The Eurocom 780W AC adapter behaves quite oddly here, as it has a rated output of 39 A and a maximum output of 45 A for 25 ms. However, we were able to draw 50 A from the unit, which is nearly 1000 Watts, for several minutes without triggering the OCP/OPP protection. The PSU did not show any serious signs of stress or overheating over that time, nor poor electrical performance. The OPP protection triggers immediately once the load is greater than 50.3 A – and also immediately resets and restarts the PSU when the load drops below 50.2A. It would seem that this platform was initially designed to be significantly more powerful and the OEM “forgot” to adjust the OCP/OPP trigger points.
The Eurocom 780W AC adapter melds raw power with innovation, presenting a piece that's as formidable as it is intriguing. With its substantial weight and metallic edges, it demands respect and caution, especially on delicate surfaces. However, its weight is justified by the impressive power output it delivers, making it a powerhouse that somewhat overshadows its bulky, heavy-set design. The inclusion of a display for monitoring performance is a smart touch, though its accuracy leaves room for improvement.
On the inside, Eurocom doesn't skimp on quality. The adapter's internals are a testament to careful selection and engineering, closely mirroring the complexity and efficiency of high-end PC PSUs. Its cooling system, though compact, functions well and provides good performance without compromising on noise levels — at least under most loads. That said, the adapter's noise profile at maximum load might not be everyone's cup of tea, hinting at a balance yet to be perfected between power and tranquility.
Overall, Eurocom's 780W AC adapter boasts commendable efficiency and electrical performance. But as a premium-priced product – a complete unit and cable will set you back at least $429 – it could benefit from a touch more finesse, particularly in terms of user safety and operational noise at high loads. Otherwise, I'm personally a bit surprised that Eurocom isn't offering a open-ended cable for DIY enthusiasts, which could broaden its appeal and utility. Such an addition would not only cater to a wider audience but also underscore Eurocom's commitment to versatility and innovation.
In sum, while the adapter stands out for its power and performance, there's also a clear avenue for Eurocom to enhance its appeal through minor, yet impactful, improvements.
When JEDEC released its DDR5 specification (JESD79) back in 2020, the standard setting organization defined precise specs for modules with speed bins of up to 6400 MT/s, while leaving the spec open to further expansions with faster memory as technology progressed. Now, a bit more than three-and-a-half years later, and the standards body and its members are gearing up to release a faster generation of DDR5 memory, which is being laid out in the newly updated JESD79-JC5 specification. The latest iteration of the DDR5 spec defines official DDR timing specifications up to 8800 MT/s, as well as adding some new features when it comes to security.
Diving in, the new specification outlines settings for memory chips (on all types of memory modules) with data transfer rates up to 8800 MT/s (AKA DDR5-8800). This suggests that all members of the JESD79 committee that sets the specs for DDR5 — including memory chip makers and memory controller designers — agree that DDR5-8800 is a viable extension of the DDR5 specification both from performance and cost point of view. Meanwhile, the addition of higher speed bins is perhaps enabled by another JEDEC feature introduced in this latest specification, which is the Self-Refresh Exit Clock Sync for I/O training optimization.
| JEDEC DDR5-A Specifications | |||||||
| AnandTech | Data Rate MT/s |
CAS Latency (cycles) | Absolute Latency (ns) | Peak BW GB/s |
|||
| DDR5-3200 | A | 3200 | 22 | 22 | 22 | 13.75 | 25.6 |
| DDR5-3600 | A | 3600 | 26 | 26 | 26 | 14.44 | 28.8 |
| DDR5-4000 | A | 4000 | 28 | 28 | 28 | 14 | 32 |
| DDR5-4400 | A | 4400 | 32 | 32 | 32 | 14.55 | 35.2 |
| DDR5-4800 | A | 4800 | 34 | 34 | 34 | 14.17 | 38.4 |
| DDR5-5200 | A | 5200 | 38 | 38 | 38 | 14.62 | 41.6 |
| DDR5-5600 | A | 5600 | 40 | 40 | 40 | 14.29 | 44.8 |
| DDR5-6000 | A | 6000 | 42 | 42 | 42 | 14 | 48 |
| DDR5-6400 | A | 6400 | 46 | 46 | 46 | 14.38 | 51.2 |
| DDR5-6800 | A | 6800 | 48 | 48 | 48 | 14.12 | 54.4 |
| DDR5-7200 | A | 7200 | 52 | 52 | 52 | 14.44 | 57.6 |
| DDR5-7600 | A | 7600 | 54 | 54 | 54 | 14.21 | 60.8 |
| DDR5-8000 | A | 8000 | 56 | 56 | 56 | 14 | 64.0 |
| DDR5-8400 | A | 8400 | 60 | 60 | 60 | 14.29 | 67.2 |
| DDR5-8800 | A | 8800 | 62 | 62 | 62 | 14.09 | 70.4 |
When it comes to the JEDEC standard for DDR5-8800, it sets relatively loose timings of CL62 62-62 for A-grade devices and CL78 77-77 for lower-end C-grade ICs. Unfortunately, the laws of physics driving DRAM cells have not improved much over the last couple of years (or decades, for that matter), so memory chips still must operate with similar absolute latencies, driving up the relative CAS latency. In this case 14ns remains the gold standard, with CAS latencies at the new speeds being set to hold absolute latencies around that mark. But in exchange for systems willing to wait a bit longer (in terms of cycles) for a result, the new spec improves the standard's peak memory bandwidth by 37.5%.
This of course is just the timings set in the JEDEC specification, which is primarily of concern for server vendors. So we'll have to see just how much harder consumer memory manufacturers can push things for their XMP/EXPO-profiled memory. Extreme overclockers are already hitting speeds as high as 11,240 MT/s with current-generation DRAM chips and CPUs, so there may be some more headroom to play with in the next generation.
Meanwhile, on the security front, the updated spec makes a couple of changes that have been put in place seemingly to address rowhammer-style exploits. The big item here is Per-Row Activation Counting (PRAC), which true to its name, enables DDR5 to keep a count of how often a row has been activated. Using this information, memory controllers can then determine if a memory row has been excessively activated and is at risk of causing a neighboring row's bits to flip, at which point they can back off to let the neighboring row properly refresh and the data re-stabilize.
Notably here, the JEDEC press release doesn't use the rowhammer name at any point (unfortunately, we haven't been able to see the specification itself). But based on the description alone, this is clearly intended to thwart rowhammer attacks, since these normally operate by forcing a bit flip between refreshes through a large number of activations.
Digging a bit deeper, PRAC seems to be based on a recent Intel patent, Perfect Row Hammer Tracking with Multiple Count Increments (US20220121398A1), which describes a very similar mechanism under the name "Perfect row hammer tracking" (PRHT). Notably, the Intel paper calls out that this technique has a performance cost associated with it because it increases the overall row cycle time. Ultimately, as the vulnerability underpinning rowhammer is a matter of physics (cell density) rather than logic, it's not too surprising to see that any mitigation of it comes with a cost.
The updated DDR5 specification also deprecates support for Partial Array Self Refresh (PASR) within the standard, citing security concerns. PASR is primarily aimed at power efficiency for mobile memory to begin with, and as a refresh-related technology, presumably overlaps some with rowhammer – be it a means to attack memory, or an obstruction to defending against rowhammer. Either way, with mobile devices increasingly moving to low-power optimized LPDDR technologies anyhow, the depreciation of PASR does not immediately look like a major concern for consumer devices.
SK hynix and TSMC announced early on Friday that they had signed a memorandum of understanding to collaborate on developing the next-generation HBM4 memory and advanced packaging technology. The initiative is designed to speed up the adoption of HBM4 memory and solidify SK hynix's and TSMC's leading positions in high-bandwidth memory and advanced processor applications.
The primary focus of SK hynix's and TSMC's initial efforts will be to enhance the performance of the HBM4 stack's base die, which (if we put it very simply) acts like an ultra-wide interface between memory devices and host processors. With HBM4, SK hynix plans to use one of TSMC's advanced logic process technologies to build base dies to pack additional features and I/O pins within the confines of existing spatial constraints.
This collaborative approach also enables SK hynix to customize HBM solutions to satisfy diverse customer performance and energy efficiency requirements. SK hynix has been touting custom HBM solutions for a while, and teaming up with TSMC will undoubtedly help with this.
"TSMC and SK hynix have already established a strong partnership over the years. We've worked together in integrating the most advanced logic and state-of-the art HBM in providing the world's leading AI solutions," said Dr. Kevin Zhang, Senior Vice President of TSMC's Business Development and Overseas Operations Office, and Deputy Co-Chief Operating Officer. "Looking ahead to the next-generation HBM4, we're confident that we will continue to work closely in delivering the best-integrated solutions to unlock new AI innovations for our common customers."
Furthermore, the collaboration extends to optimizing the integration of SK hynix's HBM with TSMC's CoWoS advanced packaging technology. CoWoS is among the most popular specialized 2.5D packaging process technologies for integrating logic chips and stacked HBM into a unified module.
For now, it is expected that HBM4 memory will be integrated with logic processors using direct bonding. However, some of TSMC's customers might prefer to use an ultra-advanced version of CoWoS to integrate HBM4 with their processors.
"We expect a strong partnership with TSMC to help accelerate our efforts for open collaboration with our customers and develop the industry's best-performing HBM4," said Justin Kim, President and the Head of AI Infra at SK hynix. "With this cooperation in place, we will strengthen our market leadership as the total AI memory provider further by beefing up competitiveness in the space of the custom memory platform."
AMD is looking to drive the AI PC market with options across multiple product lines, which aren't limited to consumer processors. While primarily designed for the commercial sector, AMD has announced the Ryzen Pro 8000 'Phoenix' series of APUs for desktops, which AMD claims is the first professional-grade CPU to include an NPU designed to provide on-chip AI neural processing capabilities. AMD has also announced the Ryzen Pro 8040 'Hawk Point' series of mobile processors designed for commercial laptops and notebooks.
AMD's Ryzen Pro 8000 and Ryzen Pro 8040 series processors come with support from AMD's Pro Manageability and AMD Pro Business Ready suites and are built with AMD's current generation Zen 4 cores. The Ryzen Pro 8000 and Ryzen Pro 8040 series processors are similar to their consumer-level counterparts. However, they have additional security features such as AMD Memory Guard, AMD Secure Processor, and Microsoft Pluton.
Touching on the differentiating factors between the non-Pro-consumer chips and the Ryzen Pro series, there is plenty for the commercial and enterprise market regarding security. In what is a first, the Ryzen Pro 8000 series is the first desktop platform to integrate Microsoft Pluton security features designed to protect when connecting to the cloud. Other features include AMD Memory Guard, which encrypts login credentials, keys, and text files stored in the DRAM. AMD Pro Security ties the AMD Zen 4 shadow stack and other layers in directly with the software stack, which, in this case, is Microsoft Windows 11 OS security.
Another notable feature that AMD is hammering home is the on-chip AI capabilities of the included Ryzen AI neural processor unit (NPU), which allows enterprises to run AI workloads locally to mitigate privacy concerns by transferring data to and from the cloud. Although the current generation of NPUs embedded into processors are limited in what they can do, Ryzen AI is a driving factor within the AI PC, as manufacturers and SDVs are looking to utilize AI-accelerated features built into software, such as Microsoft with their AI-powered Copilot tool.
Although there are requirements that now must be met to ensure a PC is considered an 'AI PC,' Microsoft announced that their AI PC requirement is 45 TOPS of performance from the NPU alone, which none of the current generation of chips from AMD and Intel currently meet. In the desktop space, AMD currently has the lead as Intel has presently no offerings with an NPU, although, in the mobile space, AMD with their Ryzen 8040 (Hawk Point) and Intel with their Meteor Lake processors provide plenty of choice for users.
| AMD Ryzen Pro 8000 Series (Zen 4) | ||||||
| AnandTech | Cores Threads |
Base Freq |
Boost Freq |
L3 Cache |
iGPU |
TDP |
| Ryzen 7 Pro 8700G | 8C / 16T | 4200 | 5100 | 16 MB | R780M (12 CUs) | 45-65 W |
| Ryzen 7 Pro 8700GE | 8C / 16T | 3650 | 5100 | 16 MB | R780M (12 CUs) | 35 W |
| Ryzen 5 Pro 8600G | 6C / 12T | 4350 | 5000 | 16 MB | R760M (8 CUs) | 45-65 W |
| Ryzen 5 Pro 8500G | 6C / 12T | 3550 | 5000 | 16 MB | R740M (4 CUs) | 45-65 W |
| Ryzen 5 Pro 8600GE | 6C / 12T | 3900 | 5000 | 16 MB | R760M (8 CUs) | 35 W |
| Ryzen 5 Pro 8500GE | 6C / 12T | 3400 | 5000 | 16 MB | R740M (4 CUs) | 35 W |
| Ryzen 3 Pro 8300G | 4C / 8T | 3450 | 4900 | 8 MB | R740M (4 CUs) | 45-65 W |
| Ryzen 3 Pro 8300GE | 4C / 8T | 3500 | 4900 | 8 MB | R740M (4 CUs) | 35 W |
Looking at the AMD Ryzen Pro 8000 series, AMD has announced eight new processors that include the same specifications as the non-Pro Ryzen 8000G APU counterparts. Two primary types of Ryzen Pro 8000 processors are set to be available: four with a configurable TDP of between 45 and 65 W and four with a flat TDP of 35 W for lower-powered environments. Leading the line-up is the Ryzen 7 Pro 8700G, which is identical in core specifications to the Ryzen 7 8700G APU, and has an 8C/16T (Zen 4) configuration with a base frequency of 4.2 GHz and a boost frequency of up to 5.1 GHz.
Even the Ryzen 7 Pro 8700GE, which is the 35 W version, has a 5.1 GHz boost frequency, although it has a slower base clock of 3.65 GHz. Both models have 16 MB of L3 cache, including AMD's integrated Radeon 780M (12 CUs) mobile graphics. All of the eight Ryzen Pro 8000 series models range from 4C/8T offerings with 8 MB of L3 cache and 4.9 GHz boost clocks, 6C/12T models with 5.0 GHz boost clocks and 16 MB of L3 cache, and those as mentioned above 8700/8700GE with 8C/16T.
While we take all performance figures given by manufacturers and vendors with a pinch of salt, AMD claims their Ryzen Pro 8000 series offers up to 19% better performance than Intel's 14th-gen Core series processors. AMD's match-up is the Ryzen 7 Pro 8700G vs. the Intel Core i7-14700, with AMD claiming a 47% victory in the Passmark 11 benchmark and 3X the graphics performance in 3D Mark Time Spy. This isn't entirely surprising because the Ryzen 7 Pro 8700G benefits from integrated RDNA3 graphics and AMD's Zen 4 cores.
| AMD Ryzen Pro 8040 Series (Zen 4) | ||||||
| AnandTech | Cores Threads |
Base Freq |
Boost Freq |
L3 Cache |
iGPU | TDP |
| Ryzen 9 Pro 8945HS | 8C / 16T | 4000 | 5200 | 16 MB | 12 | 35-54 W |
| Ryzen 7 Pro 8845HS | 8C / 16T | 3800 | 5100 | 16 MB | 12 | 35-54 W |
| Ryzen 7 Pro 8840HS | 8C / 16T | 3300 | 5100 | 16 MB | 12 | 20-28 W |
| Ryzen 5 Pro 8645HS | 6C / 12T | 4300 | 5000 | 16 MB | 8 | 35-54 W |
| Ryzen 5 Pro 8640HS | 6C / 12T | 3500 | 4900 | 16 MB | 8 | 20-28 W |
| Ryzen 7 Pro 8840U | 8C / 16T | 3300 | 5100 | 16 MB | 12 | 15-28 W |
| Ryzen 5 Pro 8640U | 6C / 12T | 3500 | 4900 | 16 MB | 8 | 15-28 W |
| Ryzen 5 Pro 8540U* | 6C / 12T | 3200 | 4900 | 16 MB | 4 | 15-28 W |
| *Ryzen 5 Pro 8540U is the only chip without AMD's Ryzen AI NPU | ||||||
Moving onto AMD's latest Ryzen Pro 8040 processors for the mobile market, AMD has refreshed their Hawk Point family for the enterprise market. AMD has eight new processors, which are segmented into two families, the HS series and the U series. The HS series has five new chips, which range from 6C/12T up to 8C/16T, all with varying levels of clock speed and TDPs. At the top of the line-up is the Ryzen 9 Pro 8945HS, which is a direct replacement for the Ryzen 9 Pro 7940HS, and as such, it comes with the same 4.0 GHz base clock and 5.2 GHz boost clocks.
Pivitong to TDP, AMD offers the Ryzen 9 Pro 8945HS, Ryzen 7 Pro 8845HS, and Ryzen 5 Pro 8645HS with a configurable TDP of between 35 and 54 W. In contrast, the Ryzen 7 Pro 8840HS and the Ryzen 5 Pro 8640HS are designed for lower-powered laptops with a cTDP of 20-28 W. Regarding cache, all of the announced Ryzen Pro 8040 series models come with 16 MB of L3 Cache. At the same time, specifications such as the integrated graphics and clock speeds all correspond to the consumer line-up, the Ryzen 8040 series.
AMD's in-house performance figures show the Ryzen 7 Pro 8840U at 15 W performing better than Intel's Core Ultra 7 165H at 28 W. Still, as we always do with performance figures provided by vendors, take these with a pinch of salt. AMD claims a 30% combined increase in performance across the board in workloads, including Geekbench v6, Blender, PCMark 10, PCMark Night Raid, and UL Procyon. While there are plenty of different areas where performance gains and losses can be achieved, AMD does claim that their Ryzen 9 Pro 8945HS at 45 W vs. the Intel Core Ultra 9 185H at 45 W is 50% better in Topaz Labs Video AI Gaia 4X software; they did both use discrete graphics in this test according to AMD's slide deck.
The other notable thing is that all of the Ryzen Pro 8040 series processors, except the bottom SKU, the Ryzen 5 Pro 8540U, come with AMD's Ryzen AI NPU integrated into the silicon. While the AI PC ecosystem is still growing, AMD and over 150+ ISVs look to continue the trend that AI will power more software features in the future than we've seen so far. We are still in the infancy stage of the ecosystem despite much of the marketing targeting the AI functionality, but as we see higher-performing NPUs coming in the next generation of chips, at least ones that can match Microsoft 45 NPU TOPS requirement to run Copilot locally, much of the benefit of the NPU is currently down to how much power can be saved.
The introduction of the Ryzen Pro 8000/8040 series completes AMD's commercial client platform, along with the readily available Ryzen Threadripper Pro 7000-WX series for commercial and professional workstations. What sets these AMD Ryzen Pro series processors apart from the consumer (non-Pro) variants is support for the AMD Pro Manageability toolkit, which includes features such as cloud-based remote manageability to enable off-site IT technicians the ability to access devices remotely, as well WPA3 SAE encryption, which provides client-to-cloud protection for enterprises over shared networks.
AMD has not announced when the Ryzen Pro 8000 series APUs or the Ryzen Pro 8040 mobile chips will be available for purchase. However, we expect a wide array of OEMs, such as HP and Lenovo, to be already in the process of readying solutions that should hit the market soon.
Taiwan Semiconductor Manufacturing Co. this week released its financial results for Q1 2024. Due to a rebound in demand for semiconductors, the company garned $18.87 billion in revenue for the quarter, which is up 12.9% year-over-year, but a decline of 3.8% quarter-over-quarter. The company says that in increase in demand for HPC processors (which includes processors for AI, PCs, and servers) drove its revenue rebound in Q1, but surprisingly, revenue share of TSMC's flagship N3 (3nm-class) process technology declined steeply quarter-over-quarter.
"Our business in the first quarter was impacted by smartphone seasonality, partially offset by continued HPC-related demand," said Wendell Huang, senior VP and chief financial officer of TSMC. "Moving into second quarter 2024, we expect our business to be supported by strong demand for our industry-leading 3nm and 5nm technologies, partially offset by continued smartphone seasonality."
In the first quarter of 2024, N3 wafer sales accounted for 9% of the foundry's revenue, down from 15% in Q4 2023, and up from 6% in Q3 2023. In terms of dollars, TSMC's 3nm production brought in around $1.698 billion, which is lower than $2.943 billion in the previous quarter. Meanwhile, TSMC's other advanced process technologies increased their revenue share: N5 (5 nm-class) accounted for 37% (up from 35%), and N7 (7 nm-class) commanded 19% (up from 17%). Though both remained relatively flat in terms of revenue, at $6.981 billion and $3.585 billion, respectively.
Generally, advanced technology nodes (N7, N5, N3) generated 65% of TSMC's revenue (down 2% from Q4 2023), while the broader category of FinFET-based process technologies contributed 74% to the company's total wafer revenue (down 1% from the previous quarter).
TSMC itself attributes the steep decline of N3's contribution to seasonally lower demand for smartphones in the first quarter as compared to the fourth quarter, which may indeed be the case as demand for iPhones typically slowdowns in Q1. Along those lines, there have also been reports about a drop in demand for the latest iPhones in China.
But even if A17 Pro production volumes are down, Apple remains TSMC's lead customer for N3B, as the fab also produces their M3, M3 Pro, and M3 Max processors on the same node. These SoCs are larger in terms of die sizes and resulting costs, so their contribution to TSMC's revenue should be quite substantial.
"Moving on to revenue contribution by platform. HPC increased 3% quarter-over-quarter to account for 46% of our first quarter revenue," said Huang. "Smartphone decreased 16% to account for 38%. IoT increased 5% to account for 6%. Automotive remained flat and accounted for 6%, and DCE increased 33% to account for 2%."
Meanwhile, as demand for AI and HPC processors will continue to increase in the coming years, TSMC expects its HPC platform to keep increasing its share in its revenue going forward.
"We expect several AI processors to be the strongest driver of our HPC platform growth and the largest contributor in terms of our overall incremental revenue growth in the next several years," said C.C. Wei, chief executive of TSMC.
This week ASML is making two very important announcements related to their progress with high numerical aperature extreme ultraviolet lithography (High-NA EUV). First up, the company's High-NA EUV prototype system at its fab in Veldhoven, the Netherlands, has printed the first 10nm patterns, which is a major milestone for ASML and their next-gen tools. Second, the company has also revealed that it's second High-NA EUV system is now out the door as well, and has been shipped to an unnamed customer.
"Our High-NA EUV system in Veldhoven printed the first-ever 10 nanometer dense lines," a statement by ASML reads. "Imaging was done after optics, sensors and stages completed coarse calibration. Next up: bringing the system to full performance. And achieving the same results in the field."
Our High NA EUV system in Veldhoven printed the first-ever 10 nanometer dense lines. ✨ Imaging was done after optics, sensors and stages completed coarse calibration.
— ASML (@ASMLcompany) April 17, 2024
Next up: bringing the system to full performance. And achieving the same results in the field. ⚙️ pic.twitter.com/zcA5V0ScUf
Alongside the system shipped to Intel at the end of 2023, ASML has retained their own Twinscan EXE:5000 scanner at their Veldhoven, Netherlands, facility, which is what the company is using for further research and development into High-NA EUV. Using that machine, the company has been able to print dense lines spaced 10 nanometers apart, which is a major milestone in photolithography development. Previously, only small-scale, experimental lab machines have been able to achieve this kind of a resolution. Eventually, High-NA EUV tools will achieve a resolution of 8 nm, which will be instrumental to build logic chips on technologies beyond 3 nm.
Intel's Twinscan EXE:5000 scanner at its D1X fab near Hillsboro, Oregon is also close behind, and its assembly is said to be nearing completion. That machine will be primarily used for Intel's own High-NA EUV R&D, with Intel slated to use its successor — the commercial-grade Twinscan EXE:5200 — to produce its chips on its Intel 14A (1.4 nm-class) in mass quantities in 2026 – 2027.
But Intel will not be the only chipmaker that gets to experiment with a High-NA EUV scanner for very long. As revealed by ASML, the company recently started shipping another Twinscan EXE:5000 machine to yet another customer. The fab tool maker is not disclosing the client, but previously it has said that all of leading logic and memory producers are in the process of procuring High-NA tools for R&D purposes, so the list of 'suspects' is pretty short.
"Regarding High-NA, or 0.55 NA EUV, we shipped our first system to a customer and this system is currently under installation," said Christophe Fouquet, chief business officer of ASML, at the company's earnings conference call with analysts and investors. "We started to ship the second system this month and its installation is also about to start."
While Intel plans to adopt High-NA EUV tools ahead of the industry, other chipmakers seem to a bit more cautious and plan to rely on risky yet already known Low-NA EUV double patterning method for production a 3 nm and 2 nm. Still, regardless of the exact timing for a transition, all of the major fabs will be relying on High-NA EUV tools in due time. So all parties have an interest in how ASML's R&D turns out.
"The customer interest for our [High-NA] system lab is high as this system will help both our Logic and Memory customers prepare for High-NA insertion into their roadmaps," said Fouquet. "Relative to 0.33 NA, the 0.55 NA system provides finer resolution enabling an almost 3x increase in transistor density, at a similar productivity, in support of sub-2nm Logic and sub-10nm DRAM nodes."
While neuromorphic computing remains under research for the time being, efforts into the field have continued to grow over the years, as have the capabilities of the specialty chips that have been developed for this research. Following those lines, this morning Intel and Sandia National Laboratories are celebrating the deployment of the Hala Point neuromorphic system, which the two believe is the highest capacity system in the world. With 1.15 billion neurons overall, Hala Point is the largest deployment yet for Intel’s Loihi 2 neuromorphic chip, which was first announced at the tail-end of 2021.
The Hala Point system incorporates 1152 Loihi 2 processors, each of which is capable of simulating a million neurons. As noted back at the time of Loihi 2’s launch, these chips are actually rather small – just 31 mm2 per chip with 2.3 billion transistors each, as they’re built on the Intel 4 process (one of the only other Intel chips to do so, besides Meteor Lake). As a result, the complete system is similarly petite, taking up just 6 rack units of space (or as Sandia likes to compare it to, about the size of a microwave), with a power consumption of 2.6 kW. Now that it’s online, Hala Point has dethroned the SpiNNaker system as the largest disclosed neuromorphic system, offering admittedly just a slightly larger number of neurons at less than 3% of the power consumption of the 100 kW British system.
A Single Loihi 2 Chip (31 mm2)
Hala Point will be replacing an older Intel neuromorphic system at Sandia, Pohoiki Springs, which is based on Intel’s first-generation Loihi chips. By comparison, Hala Point offers ten-times as many neurons, and upwards of 12x the performance overall,
Both neuromorphic systems have been procured by Sandia in order to advance the national lab’s research into neuromorphic computing, a computing paradigm that behaves like a brain. The central thought (if you’ll excuse the pun) is that by mimicking the wetware writing this article, neuromorphic chips can be used to solve problems that conventional processors cannot solve today, and that they can do so more efficiently as well.
Sandia, for its part, has said that it will be using the system to look at large-scale neuromorphic computing, with work operating on a scale well beyond Pohoiki Springs. With Hala Point offering a simulated neuron count very roughly on the level of complexity of an owl brain, the lab believes that a larger-scale system will finally enable them to properly exploit the properties of neuromorphic computing to solve real problems in fields such as device physics, computer architecture, computer science and informatics, moving well beyond the simple demonstrations initially achieved at a smaller scale.
One new focus from the lab, which in turn has caught Intel’s attention, is the applicability of neuromorphic computing towards AI inference. Because the neural networks themselves behind the current wave of AI systems are attempting to emulate the human brain, in a sense, there is an obvious degree of synergy with the brain-mimicking neuromorphic chips, even if the algorithms differ in some key respects. Still, with energy efficiency being one of the major benefits of neuromorphic computing, it’s pushed Intel to look into the matter further – and even build a second, Hala Point-sized system of their own.
According to Intel, in their research on Hala Point, the system has reached efficiencies as high as 15 TOPS-per-Watt at 8-bit precision, albeit while using 10:1 sparsity, making it more than competitive with current-generation commercial chips. As an added bonus to that efficiency, the neuromorphic systems don’t require extensive data processing and batching in advance, which is normally necessary to make efficient use of the high density ALU arrays in GPUs and GPU-like processors.
Perhaps the most interesting use case of all, however, is the potential for being able to use neuromorphic computing to enable augmenting neural networks with additional data on the fly. The idea behind this being to avoid re-training, as current LLMs require, which is extremely costly due to the extensive computing resources required. In essence, this is taking another page from how brains operate, allowing for continuous learning and dataset augmentation.
But for the moment, at least, this remains a subject of academic study. Eventually, Intel and Sandia want systems like Hala Point to lead to the development of commercial systems – and presumably, at even larger scales. But to get there, researchers at Sandia and elsewhere will first need to use the current crop of systems to better refine their algorithms, as well as better figure out how to map larger workloads to this style of computing in order to prove their utility at larger scales.
Samsung today has announced that they have developed an even faster generation of LPDDR5X memory that is set to top out at LPDDR5X-10700 speeds. The updated memory is slated to offer 25% better performance and 30% greater capacity compared to existing mobile DRAM devices from the company. The new chips also appear to be tangibly faster than Micron's LPDDR5X memory and SK hynix's LPDDR5T chips.
Samsung's forthcoming LPDDR5X devices feature a data transfer rate of 10.7 GT/s as well as maximum capacity per stack of 32 GB. This allows Samsung's clients to equip their latest smartphones or laptops with 32 GB of low-power memory using just one DRAM package, which greatly simplifies their designs. Samsung says that 32 GB of memory will be particularly beneficial for on-device AI applications.
Samsung is using its latest-generation 12nm-class DRAM process technology to make its LPDDR5X-10700 devices, which allows the company to achieve the smallest LPDDR device size in the industry, the memory maker said.
In terms of power efficiency, Samsung claims that they have integrated multiple new power-saving features into the new LPDDR5X devices. These include an optimized power variation system that adjusts energy consumption based on workload, and expanded intervals for low-power mode that extend the periods of energy saving. These innovations collectively enhance power efficiency by 25% compared to earlier versions, benefiting mobile platforms by extending battery life, the company said.
“As demand for low-power, high-performance memory increases, LPDDR DRAM is expected to expand its applications from mainly mobile to other areas that traditionally require higher performance and reliability such as PCs, accelerators, servers and automobiles,” said YongCheol Bae, Executive Vice President of Memory Product Planning of the Memory Business at Samsung Electronics. “Samsung will continue to innovate and deliver optimized products for the upcoming on-device AI era through close collaboration with customers.”
Samsung plans to initiate mass production of the 10.7 GT/s LPDDR5X DRAM in the second half of this year. This follows a series of compatibility tests with mobile application processors and device manufacturers to ensure seamless integration into future products.
Iceberg Thermal Inc. is one of the newer players in the PC cooling market. The company was founded in 2019 by an experienced team of designers and engineers setting off on their own, aiming to deliver a wide range of PC cooling products to industrial and commercial users alike. They only have a handful of retails products currently available, with the vast majority of them being CPU air coolers, but they have just launched their first liquid cooler products, the IceFLOE Oasis series.
In today’s review, we are having a look at the IceFLOE Oasis 360mm AIO (All-In-One) CPU cooler, the larger of the company's two recently-released liquid coolers. The IceFLOE Oasis CPU cooler targets the high-performance PC cooling market with a sub-$100 price point, aiming to deliver the performance needed to effectively cool a power-hungry processor without being a drain on the wallet in the process. This cooler features a 360mm radiator for an ample heat dissipation area, as well as housing for three high-airflow 120 mm fans. The IceFLOE Oasis supports a wide range of Intel and AMD socket types, making it compatible with a broad spectrum of CPUs. Additionally, it offers advanced RGB lighting, allowing users to customize the aesthetic of their cooling system.
Samsung Electronics this week was awarded up to $6.4 billion from the U.S. government under the CHIPS and Science Act to build its new fab complex in Taylor, Texas. This is the third major award under the act in the last month, with all three leading-edge fabs – Intel, TSMC, and now Samsung – receiving multi-billion dollar funding packages under the domestic chip production program. Overall, the final price tag on Samsung's new fab complex is expected to reach $40 billion by the time it's completed later this decade.
Samsung's CHIPS Act funding was announced during a celebratory event attended by U.S. Secretary of Commerce Gina Raimondo and Samsung Semiconductor chief executive Kye Hyun Kyung. During the event, Kyung outlined the strategic goals of the expansion, emphasizing that the additional funding will not only increase production capacity but also strengthen the entire local semiconductor ecosystem. Samsung plans to equip its fab near Taylor, Texas, with the latest wafer fab tools to produce advanced chips. The Financial Times reports that Samsung aims to produce semiconductors on its 2nm-class process technology starting 2026, though for now this is unofficial information.
"I am pleased to announce a preliminary agreement between Samsung and the Department of Commerce to bring Samsung's advanced semiconductor manufacturing and research and development to Texas," said Joe Biden, the U.S. president, in a statement. "This announcement will unleash over $40 billion in investment from Samsung, and cement central Texas's role as a state-of-the-art semiconductor ecosystem, creating at least 21,500 jobs and leveraging up to $40 million in CHIPS funding to train and develop the local workforce. These facilities will support the production of some of the most powerful chips in the world, which are essential to advanced technologies like artificial intelligence and will bolster U.S. national security."
Samsung has been a significant contributor to the Texas economy for decades, starting chip manufacturing in the U.S. in 1996. With previous investments totaling $18 billion in its Austin operations, Samsung's expansion into Taylor with an additional investment of at least $17 billion underscores its role as one of the largest foreign direct investors in U.S. history. The total expected investment in the new fab surpasses $40 billion, making it one of the largest for a greenfield project in the nation and transforming Taylor into a major hub for semiconductor manufacturing.
The CEO highlighted the substantial economic impact of Samsung's operations, noting a nearly double increase in regional economic output from $13.6 billion to $26.8 billion between 2022 and 2023. The ongoing expansion is projected to further stimulate economic growth, create thousands of jobs, and enhance the community's overall development.
“We are not just expanding production facilities; we’re strengthening the local semiconductor ecosystem and positioning the U.S. as a global semiconductor manufacturing destination.” said Kyung. “To meet the expected surge in demand from U.S. customers, for future products like AI chips, our fabs will be equipped for cutting-edge process technologies and help bring security to the U.S. semiconductor supply chain.”
Samsung is also committed to environmental sustainability and workforce development. The company plans to operate using 100% clean energy and incorporate advanced water management technologies. Additionally, it is investing in education and training programs to develop a new generation of semiconductor professionals. These initiatives include partnerships with educational institutions and programs tailored for military veterans.
In his remarks, Kyung expressed gratitude to President Biden, Secretary Raimondo, and other governmental and community supporters for their ongoing support. This collaborative effort between Samsung and various levels of government, as well as the local community, is pivotal in advancing America's semiconductor industry and ensuring its global competitiveness.
"Today’s announcement will help Samsung bring more semiconductor production, innovation, and jobs to U.S. shores, reinforcing America’s economy, competitiveness, and critical chip supply chains," a statememt by the Semiconductor Industry Associate reads. "We applaud Samsung for investing boldly in U.S.-based manufacturing and salute the U.S. Commerce Department for making significant headway in implementing the CHIPS Act’s manufacturing incentives and R&D programs. We look forward to continuing to work with leaders in government and industry to ensure the CHIPS Act remains on track to help reinvigorate U.S. chip manufacturing and research for many years to come."
With NVIDIA’s Turing architecture turning six years old this year, the company has been retiring many of the remaining Turing products from its video card lineup. And today that spirit of spring cleaning is coming to the entry-level segment of NVIDIA’s professional visualization lineup, where NVIDIA is introducing a pair of new desktop cards based on their low-end Ampere hardware.
The new RTX A1000 and RTX A400 cards will be replacing the T1000/T600/T400 lineup, which was released three years ago in 2021. The new cards slot into the same entry-level category and finally finish fleshing out the RTX A series of proviz cards, offering NVIDIA’s Ampere-generation professional graphics technologies in the lowest-power, lowest-performance, lowest-cost configuration possible.
Notably, since the entry-level T-series were based on NVIDIA’s feature-limited TU11x silicon, which lacked ray tracing and tensor core support – the basis of NVIDIA’s RTX technologies and associated branding – this marks the first time these technologies will be available in NVIDIA’s entry-level desktop proviz cards. And accordingly, these are being promoted to RTX-branded video cards, ending the odd overlap with NVIDIA’s compute cards, which never carry RTX branding.
It goes without saying that as low-end cards, the ray tracing performance of either part is nothing to write home about, but it gives NVIDIA’s current proviz lineup a consistent set of graphics features from top to bottom.
| NVIDIA Professional Visualization Card Specification Comparison | ||||||
| A1000 | A400 | T1000 | T400 | |||
| CUDA Cores | 2304 | 768 | 896 | 384 | ||
| Tensor Cores | 72 | 24 | N/A | N/A | ||
| Boost Clock | 1460MHz | 1755MHz | 1395MHz | 1425MHz | ||
| Memory Clock | 12Gbps GDDR6 | 12Gbps GDDR6 | 10Gbps GDDR6 | 10Gbps GDDR6 |
||
| Memory Bus Width | 128-bit | 64-bit | 128-bit | 64-bit | ||
| VRAM | 8GB | 4GB | 8GB | 4GB | ||
| Single Precision | 6.74 TFLOPS | 2.7 TFLOPS | 2.5 TFLOPS | 1.09 TFLOPS | ||
| Tensor Performance | 53.8 TFLOPS | 21.7 TFLOPS | N/A | N/A | ||
| TDP | 50W | 50W | 50W | 30W | ||
| Cooling | Active, SS | Active, SS | Active, SS | Active, SS | ||
| Outputs | 4x mDP 1.4a | 4x mDP 1.4a | 3x mDP 1.4a | |||
| GPU | GA107 | TU117 | ||||
| Architecture | Ampere | Turing | ||||
| Manufacturing Process | Samsung 8nm | TSMC 12nm | ||||
| Launch Date | 04/2024 | 05/2024 | 05/2021 | 05/2021 | ||
Both the A1000 and A400 are based on the same board design, with NVIDIA doing away with any pretense of physical feature differentiation this time around (T400 was missing its 4th Mini DisplayPort). This means both cards are based on the GA107 GPU, sporting different core and memory configurations.
RTX A1000 is a not-quite-complete configuration of GA107, with 2304 CUDA cores and 72 tensor cores. This is paired with 8GB of GDDR6, which runs at 12Gbps, for a total of 192GB/second of memory bandwidth. The TDP of the card is 50 Watts, matching its predecessor.
Meanwhile RTX A400 is far more cut down, offering about a third of the active hardware on the GPU itself, and half the memory bandwidth. On paper this gives it around 40% of T1000’s performance, and half the memory bandwidth – or 96GB/second. Notably, despite the hardware cut-down, the official TDP is still 50 Watts, versus the 30 Watts of its predecessor. So at this point NVIDIA will soon cease offering a desktop proviz card lower than 50 Watts.
As noted before, both cards otherwise feature the same physical design, with a half-height half-length (HHHL) board with active cooling. As you’d expect from such low-TDP cards, these are single-slot cooler designs. Both cards feature a quartet of Mini DisplayPorts, with the same DP 1.4a functionality that we’ve seen across all of NVIDIA’s products for the last several years.
Finally, video-focused users will want to make note that the A1000/A400 have slightly different video capabilities. While A1000 gets access to both of GA107’s NVDEC video decode blocks, A400 only gets access to a single block – one more cutback to differentiate the two cards. Otherwise, both video cards get access to the GPU’s sole NVENC block.
According to NVIDIA, the RTX A1000 will be available starting today through its distribution partners. Meanwhile the RTX A400 will hit distribution channels in May, and with OEMs expected to begin offering the cards as part of their pre-built systems this summer.
SK hynix is one of the few vertically integrated manufacturers in the flash-based storage market. The company is well-established in the OEM market. A few years back, they also started exploring direct end-user products. Internal SSDs (starting with the Gold S31 and Gold P31) were the first out of the door. Late last year, the company introduced the Beetle X31 portable SSD, its first direct-attached storage product. In February, a complementary product was introduced - the Tube T31 Stick SSD.
The Beetle X31 is a portable SSD with a Type-C upstream port and a separate cable. The Tube T31 is a take on the traditional thumb drive with a male Type-A interface. The size of the Beetle X31 makes the use of a bridge solution obvious. Our investigation into the Tube T31 also revealed the use of the same internal SSD, albeit with a different bridge. Read on for a detailed look at the Tube T31, including an analysis of its internals and evaluation of its performance consistency, power consumption, and thermal profile.
Corsair has introduced a family of registered memory modules with ECC that are designed for AMD's Ryzen Threadripper 7000 and Intel's Xeon W-2400/3400-series processors. The new Corsair WS DDR5 RDIMMs with AMD EXPO and Intel XMP 3.0 profiles will be available in kits of up to 256 GB capacity and at speeds of up to 6400 MT/s.
Corsair's family of WS DDR5 RDIMMs includes 16 GB modules operating at up to 6400 MT/s with CL32 latency as well as 32 GB modules functioning at 5600 MT/s with CL40 latency. At present, Corsair offers a quad-channel 64 GB kit (4×16GB, up to 6400 MT/s), a quad-channel 128GB kit (4×32GB, 5600 MT/s), an eight-channel 128 GB kit (8×16GB, 5600 MT/s), and an eight-channel 256 GB kit (8×32GB, 5600 MT/s) and it remains to be seen whether the company will expand the lineup.
Corsair's WS DDR5 RDIMMs are designed for AMD's TRX50 and WRX90 platforms as well as Intel's W790 platform and are therefore compatible with AMD's Ryzen Threadripper Pro 7000 and 7000WX-series as well as Intel's Xeon W-2400/3400-series CPUs. The modules feature both AMD EXPO and Intel XMP 3.0 profiles to easily set their beyond-JEDEC-spec settings and come with thin heat spreaders made of pyrolytic graphite sheet (PGS), which thermal conductivity than that of copper and aluminum of the same thickness. For now, Corsair does not disclose which RCD and memory chips its registered memory modules use.
Unlike many of its rivals among leading DIMM manufacturers, Corsair did not introduce its enthusiast-grade RDIMMs when AMD and Intel released their Ryzen Threadripper and Xeon W-series platforms for extreme workstations last year. It is hard to tell what the reason for that is, but perhaps the company wanted to gain experience working with modules featuring registered clock drivers (RCDs) as well as AMD's and Intel's platforms for extreme workstations.
The result of the delay looks to be quite rewarding: unlike modules from its competitors that either feature AMD EXPO or Intel XMP 3.0 profiles, Corsair's WS DDR5 RDIMMs come with both. While this may not be important on the DIY market where people know exactly what they are buying for their platform, this is a great feature for system integrators, which can use Corsair WS DDR5 RDIMMs both for their AMD Ryzen Threadripper and Intel Xeon W-series builds, something that greatly simplifies their inventory management.
Since Corsair's WS DDR5 RDIMMs are aimed at workstations and are tested to offer reliable performance beyond JEDEC specifications, they are quite expensive. The cheapest 64 GB DDR5-5600 CL40 kit costs $450, the fastest 64 GB DDR5-6400 CL32 kit is priced at $460, whereas the highest end 256 GB DDR5-5600 CL40 kit is priced at $1,290.
Western Digital this week is previewing the industry's first 4 TB SD card. The device is being showcased at the NAB trade show for broadcasters and content creators and will be released commercially in 2025.
Western Digital's SanDisk Extreme Pro SDUC 4 TB SD card complies with the Secure Digital Ultra Capacity standard (SDUC, which enables up to 128TB). The card uses the Ultra High Speed-I (UHS-I) interface and is rated for speed Class 10, therefore supporting a minimum speed of 10 MB/s and a maximum data transfer rate of 104 MB/s when working in UHS104 (SDR104) mode (there is a catch about performance, but more on that later). WD's SD card is also rated to meet Video Speed Class V30, supporting a minimal sequential write speed of 30 MB/s, which is believed to be good enough for 8K video recording, above and beyond the 4K video market that Western Digital is primarily aiming the forthcoming card at.
For now, Western Digital is not disclosing what NAND is in the SanDisk Extreme Pro SDUC 4 TB SD card. Given the high capacity and relatively distant 2025 release date, WD may be targetting this as one of their first products to use their forthcoming BiCS 9 NAND.
And while not listed in WD's official press release, we would be surprised if the forthcoming card didn't also support the off-spec DDR200/DDR208 mode, which allows for higher transfer rates than the UHS-I standard normally allows via double data rate signaling. Western Digital's current-generation SanDisk Extreme Pro SDXC 1 TB SD card already supports that mode, allowing it to reach read speeds as high as 170 MB/s, so it would be surprising to see the company drop it from newer products. That said, the catch with DDR208 remains the same as always: it's a proprietary mode that requires a compatible host to make use of.
Western Digital has not disclosed how much will its SanDisk Extreme Pro SDUC 4 TB SD card cost. A 1 TB SanDisk Extreme Pro card costs $140, so one can make guesses about the price of a 4 TB SD card that uses cutting-edge NAND.
AMD has recently expanded its Ryzen 8000 series by introducing the Ryzen 7 8700F and Ryzen 5 8400F processors. Initially launched in China, these chips were added to AMD's global website, signaling they are available worldwide, apparently from April 1st. Built from the recent Zen 4-based Phoenix APUs using the TSMC 4nm node as their Zen 4 mobile chips, these new CPUs lack integrated graphics. However, the Ryzen 7 8700F does include the integrated Ryzen AI NPU for added capabilities in a world currently dominated by AI and moving it directly into the PC.
The company's decision to announce these chips in China aligns with its strategy to offer Ryzen solutions at every price point in the market. Although AMD didn't initially disclose the full specifications of these F-series models, and we did reach out to the company to ask about them, they refused to discuss them with us. Their listing on the website has now been updated with a complete list of specifications and features, with everything but the price mentioned.
| AMD Ryzen 8000G vs. Ryzen 8000F Series (Desktop) Zen 4 (Phoenix) |
|||||||||
| AnandTech | Cores/Threads | Base Freq |
Turbo Freq |
GPU | GPU Freq |
Ryzen AI (NPU) |
L3 Cache (MB) |
TDP | MSRP |
| Ryzen 7 | |||||||||
| Ryzen 7 8700G | 8/16 | 4200 | 5100 | R780M 12 CUs |
2900 | Y | 16 | 65W | $329 |
| Ryzen 7 8700F | 8/16 | 4100 | 5000 | - | - | Y | 16 | 65W | ? |
| Ryzen 5 | |||||||||
| Ryzen 5 8600G | 6/12 | 4300 | 5000 | R760M 8 CUs |
2800 | Y | 16 | 65W | $229 |
| Ryzen 5 8400F | 6/12 | 4200 | 4700 | - | - | N | 16 | 65W | ? |
The Ryzen 7 8700F features an 8C/16T design, with 16MB of L3 cache and the same 65W TDP as the Ryzen 7 8700G. Although the base clock speed is 4.1 GHz, it boosts to 5.0 GHz; this is 100 MHz less on both base/boost clocks than the 8700G. Meanwhile, the Ryzen 5 8400F is a slightly scaled-down version of the Ryzen 8600G APU, with 6C/12, 16MB of L3 cache, and again has a 100 MHz reduction to base clocks compared to the 8600G. Unlike the Ryzen 5 8400F, the Ryzen 7 8700F keeps AMD's Ryzen AI NPU, adding additional capability for generative AI.
The Ryzen 5 8400F can boost up to 4.7 GHz, 300 MHz slower than the Ryzen 5 8600G. AMD also allows overclocking for these new F-series chips, which means users could potentially boost the performance of these processors to match their G-series equivalents.
Pricing details are still pending, but to remain competitive, AMD will likely need to price these CPUs below the 8700G and 8600G, as well as the Ryzen 7 7700 and Ryzen 5 7600. These CPUs offer, albeit very limited, integrated graphics and have double the L3 cache capacity, along with higher boost clocks than the 8000F series chips, so pricing is something to consider whenever pricing becomes available.
During the main keynote at Intel Vision 2024, Intel CEO Pat Gelsinger flashed a completed Lunar Lake chip off, much like EVP and General Manager of Intel's Client Computing Group (CCG) Michelle Johnston Holthaus did back at CES 2024. The contrast between the two glimpses of the Lunar Lake chip is that Pat Gelsinger gave us something juicier than just a photo op. He clarified and claimed the levels of AI performance we can expect to see when Lunar Lake launches.
According to Intel's CEO Pat Gelsinger, Lunar Lake, scheduled to be launched towards the end of this year, is set to raise the bar even further regarding on-chip AI capabilities and performance. At Intel's own Vision event, aptly named Intel Vision, current CEO of Intel Pat Gelsinger stated during his presentation that Lunar Lake will be the 'flagship SoC' for the next generation of AI PCs. Intel claims that Lunar Lake will have 3X the AI performance of their current Meteor Lake SoC, which is impressive as Meteor Lake is estimated to be running around 34 TOPS combined with the NPU, GPU, and CPU.
Factoring in the NPU within Meteor Lake, 11 of the 34 TOPS come solely from the NPU. Still, Intel claims that the NPU on Lunar Lake will hit a large 45 TOPs, akin to the Hailo-10 add-in card and similar to Qualcomm's Snapdragon X Elite processor. Factoring in the integrated graphics and the compute cores, Intel is claiming a combined total of over 100 TOPS, and with Microsoft's self-imposed guidelines of what constitutes an 'AI PC' coming in at 40 TOPS, Intel's NPU fits the bill.
Intel also alludes to how they are gaining a load of TOPS performance from the NPU, whether that be with new technologies; the NPU will likely be built in a more advanced node, perhaps Intel 18A. Another thing Intel didn't highlight was how they were measuring the TOPS performance, whether that be INT8 or INT4.
Still, one thing is clear: Intel wants to increase on-chip AI capabilities in desktop PCs and notebooks with each generation. Intel is also attempting to leverage more AI performance to help boost its goal to ship 100 million AI PCs by the end of 2025. Intel has already announced that it's shipped 5 million thus far and plans to sell another 40 million units by the end of the year.
One of the most significant talking points of the last six months in mobile computing has been Intel and their disaggregated Meteor Lake SoC architecture. Meteor Lake, along with the new Core and Core Ultra naming scheme, also heralds the dawn of their first tiled architecture for the mobile landscape on the latest Intel 4 node with Foveros packaging. In December last year, Intel unveiled their premier Meteor lake-based Core Ultra H series, with five SKUs ranging from two with 4P+8E+2LP/18T and three with 6P+8E+2LP/22T models. Since then, many vendors and manufacturers have launched notebooks capitalizing on Intel's latest multi-tiled Meteor Lake SoC architecture as the heart of power and performance, driving their latest models into 2024.
Today, we will focus on an attractive ultrabook via the ASUS Zenbook 14 OLED (UX3405MA), which features a thin and light design and is powered by Intel's latest Meteor Lake Core Ultra 7 155H processor. While much of the attention is going to come on how the Intel Core Ultra 7 155H with its 6P+8E+2LP/22T configuration and 8 Arc Xe integrated graphics cores will perform, the ASUS Zenbook 14 OLED UX3405MA has plenty of features within its sleek Ponder Blue colored shell to make it very interesting. Included is a 14" 3K (2880 x 1800) touchscreen OLED panel with a 120 Hz refresh rate, 32 GB of LPDDR5X memory (soldered), and a 1 TB NVMe M.2 SSD for storage.
In an unexpected move, Intel has announced plans to phase out the boxed versions of its enthusiasts-class 13th Generation Core 'Raptor Lake' processors. According to a product change notification (PCN) published by the company last month, Intel plans to stop shipping these desktop CPUs by late June. In its place will remain Intel's existing lineup of boxed 14th Generation Core processors, which are based on the same 'Raptor Lake' silicon and typically carry higher performance for similar prices.
Intel customers and distributors interested in getting boxed versions 13th Generation Core i5-13600K/KF, Core i7-13700K/KF, and Core i9-13900K/KF/KS 'Raptor Lake' processors with unlocked multiplier should place their orders by May 24, 2024. The company will ship these units by June 28, 2024. Meanwhile, the PCN does not mention any change to the availability of tray versions of these CPUs, which are sold to OEMs and wholesalers.
The impending discontinuation of Intel's boxed 13th Generation Core processors comes as the company's current 14th Generation product line, 'Raptor Lake Refresh' is largely a rehash of the same silicon at slightly higher clockspeeds. Case in point: all of the discontinued SKUs are based on Intel's B0 Raptor Lake silicon, which is still being used for their 14th Gen counterparts. So Intel has not discontinued producing any Raptor Lake silicon; only the number of retail SKUs is getting cut-down.
As outlined in our 14th Generation Core/Raptor Lake Refresh review, the 14th Gen chips largely make their 13th Gen counterparts redundant, offering better performance at every tier for the same list price. And with virtually all current generation motherboards supporting both generation of chips, apparently Intel feels there's little reason to keep around what's essentially older, slower SKUs of the same silicon.
Interestingly, the retirement of the enthusiast-class 13th Generation Core chips is coming before Intel discontinues their even older 12th Generation Core 'Alder Lake' processors. 12th Gen chips are still available to this day in both boxed and tray versions, and the Alder Lake silicon itself is still widely in use in multiple product families. So even though Alder Lake shares the same platform as Raptor Lake, the chips based on that silicon haven't been rendered redundant in the same way that 13th Gen Core chips have.
Ultimately, it would seem that Intel is intent on consolidating and simplifying its boxed retail chip offerings by retiring their near-duplicate SKUs. Which for PC buyers could present a minor opportunity for a deal, as retailers work to sell off their remaining 13th Gen enthusiast chips.
Following the magnitude 7.2 earthquake that struck Taiwan on April 3, 2024, there was immediate concern over what impact this could have on chip production within the country. Even for a well-prepared country like Taiwan, the tremor was the strongest quake to hit the region in 25 years, making it no small matter. But, according to research compiled by TrendForce, the impact on the production of DRAM will not be significant. The market tracking company believes that Taiwanese DRAM industry has remained largely unaffected, primarily due to their robust earthquake preparedness measures.
There are four memory makers in Taiwan: Micron, the sole member of the "big three" memory manufacturers on the island, runs two fabs. Meanwhile among the smaller players is Nanya (which has one fab), Winbond (which makes specialty memory at one fab), and PSMC (which produces specialty memory at one plant). The study found that these DRAM producers quickly resumed full operations, but had to throw away some wafers. The earthquake is estimated to have a minor effect on Q2 DRAM production, with a negligible 1% impact, TrendForce claims
In fact, as Micron is ramping up production of DRAM on its 1alpha and 1beta nm process technologies, it increases bit production of memory, which will positively affect supply of commodity DRAM in Q2 2025.
Following the earthquake, there was a temporary halt in quotations for both the contract and spot DRAM markets. However, the spot market quotations have already largely resumed, while contract prices have not fully restarted. Notably, Micron and Samsung ceased issuing quotes for mobile DRAM immediately after the earthquake, with no updates provided as of April 8th. In contrast, SK hynix resumed quotations for smartphone customers on the day of the earthquake and proposed more moderate price adjustments for Q2 mobile DRAM.
TrendForce anticipates a seasonal contract price increase for Q2 mobile DRAM of between 3% and 8%. This moderate increase is partly due to SK hynix's more restrained pricing strategy, which is likely to influence overall pricing strategies across the industry. The earthquake's impact on server DRAM primarily affected Micron's advanced fabrication nodes, potentially leading to a rise in final sale prices for Micron's server DRAM, according to TrendForce. However, the exact direction of future prices remains to be seen.
Meanwhile, DRAM fabs outside of Taiwan have none been directly affected by the quake. This includes Micron's HBM production line in Hiroshima, Japan, and Samsung's and SK hynix's HBM lines in South Korea, all of which are apparently operating with business as usual.
In general, the DRAM industry has shown resilience in the face of the earthquake, with minimal disruptions and a quick recovery. The abundant inventory levels for DDR4 and DDR5, coupled with weak demand, suggest that any slight price elevations caused by the earthquake are expected to normalize quickly. The only potential outlier here is DDR3, which is nearing the end of its commercial lifetime and production is already decreasing.
Google was among the first hyperscalers build custom silicon for its services, starting first with tensor processing units (TPUs) for its AI initiatives, and then video transcoding units (VCUs) for the YouTube service. But unlike its industry peers, the company has been slower to adopt custom CPU designs, prefering to stick to off-the-shelf chips from the major CPUs. This is finally changing at Google, with the announcement that the company has developed its own in-house datacenter CPU, the Axion.
Google's Axion processor is based on the Arm Neoverse V2 (Arm v9) platform, which is Arm's current-generation design for high-performance server CPUs, and is already employed in other chips such as NVIDIA's Grace and Amazon's Graviton4. Within Google, Axion is aimed at a wide variety of workloads, including web and app servers, data analytics, microservices, and AI training. Google claims that the Axion processors boast up to 50% higher performance and up to 60% better energy efficiency compared to current-generation x86-based processors, as well as offer a 30% higher performance compared to competing Arm-based CPUs for datacenters. Though as is increasingly common for the cryptic cloud side of Google's business, least for now the company isn't specifying what processors they're comparing Axion to in these metrics.
While Google is not disclosing core counts or the full specifications of its Axion CPUs, the company is revealing that they are incorporating their own secret sauce into the silicon in the form of the company's Titanium purpose-built microcontrollers. These microcontrollers are designed to handle basic operations like networking and security, as well as offload storage I/O processing to Hyperdisk block storage service. As a result of this offloading, virtually all of the CPU core resources should be available to actual workloads. As for the chip's memory subsystem, Axion uses conventional dual-rank DDR5 memory modules.
"Google's announcement of the new Axion CPU marks a significant milestone in delivering custom silicon that is optimized for Google's infrastructure, and built on our high-performance Arm Neoverse V2 platform," said Rene Haas, CEO of Arm. "Decades of ecosystem investment, combined with Google's ongoing innovation and open-source software contributions ensure the best experience for the workloads that matter most to customers running on Arm everywhere."
Google has previously deployed Arm-based processors for its own services, including BigTable, Spanner, BigQuery, and YouTube Ads and is ready to offer instances based on its Armv9-based Axion CPUs to its customers that can use software developed for Arm architectures.
Sources: Google, Wall Street Journal
Intel this morning is kicking off the second day of their Vision 2024 conference, the company’s annual closed-door business and customer-focused get-together. While Vision is not typically a hotbed for new silicon announcements from Intel – that’s more of an Innovation thing in the fall – attendees of this year’s show are not coming away empty handed. With a heavy focus on AI going on across the industry, Intel is using this year’s event to formally introduce the Gaudi 3 accelerator, the next-generation of Gaudi high-performance AI accelerators from Intel’s Habana Labs subsidiary.
The latest iteration of Gaudi will be launching in the third quarter of 2024, and Intel is already shipping samples to customers now. The hardware itself is something of a mixed bag in some respects (more on that in a second), but with 1835 TFLOPS of FP8 compute throughput, Intel believes it’s going to be more than enough to carve off a piece of the expansive (and expensive) AI market for themselves. Based on their internal benchmarks, the company expects to be able beat NVIDIA’s flagship Hx00 Hopper architecture accelerators in at least some critical large language models, which will open the door to Intel grabbing a larger piece of the AI accelerator market at a critical time in the industry, and a moment when there simply isn’t enough NVIDIA hardware to go around.
At Intel's Vision 2024 event, which is being held in Phoenix, AZ, has seen several key announcements. On the datacenter CPU front, Intel is using the show to unveil their newest branding for their venerable family of Xeon processors. Beginning with this year's sixth generation of processors, Intel is "evolving" the Xeon brand by retiring the "Xeon Scalable" branding in favor of Intel's new and simplified "Xeon 6" brand.
The Xeon 6 family is set to launch later this year with two primary variants: an all-performance (P) core chip codenamed Granite Rapids, and an all-efficiency (E) core chip codenamed Sierra Forest. Both of these chips will be sold under the Xeon 6 brand and sit on top of the same motherboard platform, with the Xeon 6 branding intended in part to underscore this shared platform. Though speaking of the chips themselves, at this time Intel isn't illustrating how the two sub-series of chips will be differentiated in terms of product numbers.
Over the last year, we've extensively covered Intel's Granite Rapids and Sierra Forest. For more information about Granite Rapids and Sierra Forest, here are some of our key pieces:
Intel debuted their Xeon Scalable branding in 2017 with the launch of the Xeon Platinum 8100 series, which was built using their Skylake microarchitecture. At the time Xeon Scalable replaced Intel's older Xeon E/EP/EX vX branding, resetting the generation count in the process.
Moving forward to 2024, Intel is looking to build an ecosystem befitting the current demands of technologies within key areas such as data centers, Edge, and the PC. Intel is laying the foundations for what it calls 'Intel Enterprise AI.' Using a vast array of frameworks and accelerators and working closely with partners, ISVs, and GSIs to create a large and open ecosystem, the newly branded Intel Xeon 6 platforms will be key in the enterprise market as we advance.
Intel has adopted a newer and simpler nomenclature for Granite Rapids and Sierra Forest, starting with the Intel Xeon 6 processors. Sierra Forest Xeon 6 processors are set to launch in Q2 of 2024, which include a chip featuring 288 E-cores. It will be the first product to adopt this new branding, which is designed to ease customer navigation between models. Meanwhile the Xeon 6 P-core Granite Rapids processors will come later.
Ultimately, the Xeon brand itself and what it entails (enterprise, workstation, server, and data center) isn't going anywhere. Instead, Intel is putting an increased focus on the generation number of the platform by moving it front and center, to more clearly highlight what generation of technology a part belongs to.
As mentioned, Intel's Xeon 6 processors, based on their Sierra Forest architecture, are set to launch in Q2 2024, while the Granite Rapids Xeon 6 platform is expected to come sometime in the second half of 2024.
TSMC has entered into a preliminary agreement with the U.S. Department of Commerce, securing up to $6.6 billion in direct funding and access to up to $5 billion in loans under the CHIPS and Science Act. With this latest round of support from the U.S. government, TSMC in turn will be adding a third fab to their Arizona project, with its investment in the region soaring to more than $65 billion. This move not only signifies the largest foreign direct investment in Arizona but also marks one of the biggest support packages that the U.S. government plans to make under the CHIPS Act, second only to Intel's $8.5 billion award last month.
TSMC is currently equipping its Fab 21 phase 1 and expects that it will start making chips using N4 and N5 (4 nm and 5 nm-class) process technologies in the first half of 2025. TSMC's Fab 21 phase 2 will commence operations in 2028, and will make chips on N3 and N2 (3 nm and 2 nm-class) production nodes. The newly-announced third fab (designation TBD) is set to manufacture chips on processes of 2 nm-class or beyond, with the start of production anticipated by the end of the decade.
TSMC has not announced a planned capacity for the new fab, only noting that it will be similar to the other two Arizona fabs, boasting a cleanroom space roughly twice as large as that of a typical "industry-standard logic fab." If it is sized similarly to the other Arizona fabs, then this strongly implies that the new fab will be another MegaFab-class facility – a mid-range fab producing around 25,000 wafer starts per month. TSMC does operate even larger fabs – the 100K WSPM GigaFab – though to date they've yet to build any of these outside of Taiwan.
“The CHIPS and Science Act provides TSMC the opportunity to make this unprecedented investment and to offer our foundry service of the most advanced manufacturing technologies in the United States,” said TSMC Chairman Dr. Mark Liu. “Our U.S. operations allow us to better support our U.S. customers, which include several of the world’s leading technology companies. Our U.S. operations will also expand our capability to trailblaze future advancements in semiconductor technology.”
The construction of three fabs in Arizona is poised to generate approximately 6,000 direct high-tech jobs, contributing significantly to the creation of a skilled workforce. This workforce is expected to play a crucial role in fostering a dynamic and competitive global semiconductor ecosystem. Moreover, the project is projected to create over 20,000 construction jobs, in addition to spawning tens of thousands of indirect jobs related to suppliers and consumer services.
AMD, Apple, and NVIDIA fully support TSMC's project and all of them expressed interest in using TSMC's capacities in the U.S.
“Today’s announcement highlights the strong commitment from Secretary Raimondo and the entire administration to ensure the U.S. plays a central role creating a more geographically diverse and resilient semiconductor supply chain,” said AMD Chair and CEO Lisa Su. “TSMC has a long track record of providing the leading-edge manufacturing capabilities that have enabled AMD to focus on what we do best, designing high-performance chips that change the world. We are committed to our partnership with TSMC and look forward to building our most advanced chips in U.S.”
TSMC's ventures in Arizona have encountered obstacles, such as setbacks caused by labor shortages and doubts about the U.S. governmental funding. As a result, production at the second facility has been postponed from 2026 to 2028. Moreover, Bloomberg has reported that at least one supplier for TSMC has called off its intended project in Arizona, attributing the decision to challenges in securing a workforce. The address the workforce issues, the TSMC grant includes a $50 million allocation for training of the local workforce.
In the arena of PC components, Be quiet! is a name synonymous with excellence, known for its fusion of silent functionality and exceptional performance. The company's broad range of products, from high-end power supply units (PSUs) to sophisticated cases and cooling solutions, including both air and liquid options, is crafted with a keen eye on reducing noise while maximizing efficiency. Be quiet! has earned accolades for its dedication to achieving near-silent operation across its lineup, making it a preferred choice among those in the PC enthusiast community who seek a serene computing environment. The diversity of its offerings reflects a deep understanding of the needs of tech enthusiasts and professionals alike, with each product designed to offer a blend of low noise levels and high efficiency.
Today we're looking at he Be quiet! Straight Power 12 750W PSU, a high-tier offering in Be quiet!'s PSU portfolio that exemplifies the brand's approach to product design. The Straight Power 12 series is engineered to deliver top performance and whisper-quiet operation, appealing to users who seek the optimal mix of power efficiency and sound level, without compromising on reliability and premium quality. The 750 Watt model that we are reviewing today is the weakest unit of the series, yet still enough to effortlessly power a modern gaming system with a mid-tier GPU.
SK hynix this week announced plans to build its advanced memory packaging facility in West Lafayette, Indiana. The move can be considered as a milestone both for the memory maker and the U.S., as this is the first advanced memory packaging facility in the country and the company's first significant manufacturing operation in America. The facility will be used to build next-generation types of high-bandwidth memory (HBM) stacks when it begins operations in 2028. Also, SK hynix agreed to work on R&D projects with Purdue University.
"We are excited to become the first in the industry to build a state-of-the-art advanced packaging facility for AI products in the United States that will help strengthen supply-chain resilience and develop a local semiconductor ecosystem," said SK hynix CEO Kwak Noh-Jung.
The facility will handle assembly of HBM known good stacked dies (KGSDs), which consist of multiple memory devices stacked on a base die. Furthermore, it will be used to develop next-generations of HBM and will therefore house a packaging R&D line. However, the plant will not make DRAM dies themselves, and will likely source them from SK hynix's fabs in South Korea.
The plant will require SK hynix to invest $3.87 billion, which will make it one of the most advanced semiconductor packaging facilities in the world. Meanwhile, SK hynix held the investment agreement ceremony with representatives from Indiana State, Purdue University, and the U.S. government, which indicates parties financially involved in the project, but this week's event did not disclose whether SK hynix will receive any money from the U.S. government under the CHIPS Act or other funding initiatives.
The cost of the facility significantly exceeds that of packaging facilities built by other major players in the industry, such as ASE Group, Intel, and TSMC, which highlights how significant of an investment this is for SK hnix. In fact, $3.87 billion higher than advanced packaging CapEx budgets of Intel, TSMC and Samsung in 2023, based on estimates from Yole Intelligence.
Given that the fab comes online in 2028, based on SK hynix's product roadmap we'd expect that it will be used at least in part to assemble HBM4 and HBM4E stacks. Notably, since HBM4 and HBM4E stacks are set to feature a 2048-bit interface, their packaging process will be considerably more complex than the existing 1024-bit HBM3/HBM3E packaging and will require usage of more advanced tools, which is why it is poised to be more expensive than some existing advanced packaging facilities. Due to the extremely complex 2048-bit interface, many chip designers who are going to use HBM4/HBM4E are expected to integrate it directly onto their processors using hybrid bonding and not use silicon interposers. Unfortunately, it is unclear whether the SK hynix facility will be able to offer such service.
HBM is mainly used for AI and HPC applications, so it is strategically important to have its production in the U.S. Meanwhile, actual memory dies will still need to be made elsewhere, at dedicated DRAM fabs.
In addition to support set to be provided by state and local governmens, SK hynix chose to establish its new facility in West Lafayette, Indiana, to collaborate with Purdue University as well as with Purdue's Birck Nanotechnology Center on R&D projects, which includes advanced packaging and heterogeneous integration.
SK hynix intends to work in partnership with Purdue University and Ivy Tech Community College to create training programs and multidisciplinary degree courses aimed at nurturing a skilled workforce and establishing a consistent stream of emerging talent for its advanced memory packaging facility and R&D operations.
"SK hynix is the global pioneer and dominant market leader in memory chips for AI," Purdue University President Mung Chiang said. "This transformational investment reflects our state and university's tremendous strength in semiconductors, hardware AI, and hard tech corridor. It is also a monumental moment for completing the supply chain of digital economy in our country through chips advanced packaging. Located at Purdue Research Park, the largest facility of its kind at a U.S. university will grow and succeed through innovation."
PCI-SIG this week released version 0.5 of the PCI-Express 7.0 specification to its members. This is the second draft of the spec and the final call for PCI-SIG members to submit their new features to the standard. The latest update on the development of the specification comes a couple months shy of a year after the PCI-SIG published the initial Draft 0.3 specificaiton, with the PCI-SIG using the latest update to reiterate that development of the new standard remains on-track for a final release in 2025.
PCIe 7.0 is is the next generation interconnect technology for computers that is set to increase data transfer speeds to 128 GT/s per pin, doubling the 64 GT/s of PCIe 6.0 and quadrupling the 32 GT/s of PCIe 5.0. This would allow a 16-lane (x16) connection to support 256 GB/sec of bandwidth in each direction simultaneously, excluding encoding overhead. Such speeds will be handy for future datacenters as well as artificial intelligence and high-performance computing applications that will need even faster data transfer rates, including network data transfer rates.
To achieve its impressive data transfer rates, PCIe 7.0 doubles the bus frequency at the physical layer compared to PCIe 5.0 and 6.0. Otherwise, the standard retains pulse amplitude modulation with four level signaling (PAM4), 1b/1b FLIT mode encoding, and the forward error correction (FEC) technologies that are already used for PCIe 6.0. Otherwise, PCI-SIG says that the PCIe 7.0 speicification also focuses on enhanced channel parameters and reach as well as improved power efficiency.
Overall, the engineers behind the standard have their work cut out for them, given that PCIe 7.0 requires doubling the bus frequency at the physical layer, a major development that PCIe 6.0 sidestepped with PAM4 signaling. Nothing comes for free in regards to improving data signaling, and with PCIe 7.0, the PCI-SIG is arguably back to hard-mode development by needing to improve the physical layer once more – this time to enable it to run at around 30GHz. Though how much of this heavy lifting will be accomplished through smart signaling (and retimers) and how much will be accomplished through sheer materials improvements, such as thicker printed circuit boards (PCBs) and low-loss materials, remains to be seen.
The next major step for PCIe 7.0 is finalization of the version 0.7 of specification, which is considered the Complete Draft, where all aspects must be fully defined, and electrical specifications must be validated through test chips. After this iteration of the specification is released, no new features can be added. PCIe 6.0 eventually went through 4 major drafts – 0.3, 0.5, 0.7, and 0.9 – before finally being finalized, so PCIe 7.0 is likely on the same track.
Once finalized in 2025, it should take a few years for the first PCIe 7.0 hardware to hit the shelves. Although development work on controller IP and initial hardware is already underway, that process extends well beyond the release of the final PCIe specification.
Composable disaggregated data center infrastructure promises to change the way data centers for modern workloads are built. However, to fully realize the potential of new technologies, such as CXL, the industry needs brand-new hardware. Recently, Samsung introduced its CXL Memory Module Box (CMM-B), a device that can house up to eight CXL Memory Module – DRAM (CMM-D) devices and add plenty of memory connected using a PCIe/CXL interface.
Samsung's CXL Memory Module Box (CMM-B) is the first device of this type to accommodate up to eight 2 TB E3.S CMM-D memory modules and add up to 16 TB of memory to up to three modern servers with appropriate connectors. As far as performance is concerned, the box can offer up to 60 GB/s of bandwidth (which aligns with what a PCIe 5.0 x16 interface offers) and 596 ns latency.
From a pure performance point of view, one CXL Memory Module—Box is slower than a dual-channel DDR5-4800 memory subsystem. Yet, the unit is still considerably faster than even advanced SSDs. At the same time, it provides very decent capacity, which is often just what the doctor ordered for many applications.
The Samsung CMM-B is compatible with the CXL 1.1 and CXL 2.0 protocols. It consists of a rack-scale memory bank (CMM-B), several application hosts, Samsung Cognos management console software, and a top-of-rack (ToR) switch. The device was developed in close collaboration with Supermicro, so expect this server maker to offer the product first.
Samsung's CXL Memory Module – Box is designed for applications that need a lot of memory, such as AI, data analytics, and in-memory databases, albeit not at all times. CMM-B allows the dynamic allocation of necessary memory to a system when it needs this memory and then uses DRAM with other machines. As a result, operators of datacenters can spend money on procuring expensive memory (16 TB of memory costs a lot), reduce power consumption, and add flexibility to their setups.
Rapidus, a Japan-based company developing 2nm process technology and aiming to commercialize it in 2027, will receive a huge government grant for its ongoing projects. The Japanese government will support Rapidus with subsidies totaling ¥590 billion yen ($3.89 billion). In addition to developing its 2nm production node and spending on cleanroom equipment, Rapidus will also fund the development of multi-chiplet packaging technology.
This extra funding will significantly help the company's ambitious plans. With the government's total support now at ¥920 billion ($6.068 billion), Rapidus is getting a solid push to become a significant player in the semiconductor industry. The whole project is expected to cost around ¥5 trillion ($32.983 billion), so the funding is not quite there yet. Meanwhile, the company may get enough financing with support from the Japanese government and large Japanese conglomerates like Toyota Motor and Nippon Telegraph and Telephone.
According to Atsuyoshi Koike, Rapidus's chief executive, the company is on track to start testing its production by April 2025 and aims to begin large-scale production by 2027. Commercial production of 2nm chips is set to commence sometime in 2025.
In addition to developing its 2nm fabrication process in collaboration with IBM and building its manufacturing facility, Rapidus is also working on advanced packaging technology for multi-chiplet system-in-packages (SiPs). The latest government subsidies include more than ¥50 billion ($329.85 million) for research and development in this area, the first time Japan has provided subsidies for such technologies.
It is noteworthy that Rapidus will use a section of Seiko Epson Corporation's Chitose Plant (located in Chitose City, Hokkaido) for its back-end packaging processes. This plant is near the company's fab, which is currently being built in Bibi World, an industrial park in Chitose City. This space will be dedicated to pilot-stage research and development activities.
Introspect this week introduced its M5512 GDDR7 memory test system, which is designed for testing GDDR7 memory controllers, physical interface, and GDDR7 SGRAM chips. The tool will enable memory and processor manufacturers to verify that their products perform as specified by the standard.
One of the crucial phases of a processor design bring up is testing its standard interfaces, such as PCIe, DisplayPort, or GDDR is to ensure that they behave as specified both logically and electrically and achieve designated performance. Introspect's M5512 GDDR7 memory test system is designed to do just that: test new GDDR7 memory devices, troubleshoot protocol issues, assess signal integrity, and conduct comprehensive memory read/write stress tests.
The product will be quite useful for designers of GPUs/SoCs, graphics cards, PCs, network equipment and memory chips, which will speed up development of actual products that rely on GDDR7 memory. For now, GPU and SoC designers as well as memory makers use highly-custom setups consisting of many tools to characterize signal integrity as well as conduct detailed memory read/write functional stress testing, which are important things at this phase of development. But usage of a single tool greatly speeds up all the processes and gives a more comprehensive picture to specialists.
The M5512 GDDR7 Memory Test System is a desktop testing and measurement device that is equippped with 72 pins capable of functioning at up to 40 Gbps in PAM3 mode, as well as offering a virtual GDDR7 memory controller. The device features bidirectional circuitry for executing read and write operations, and every pin is equipped with an extensive range of analog characterization features, such as skew injection with femto-second resolution, voltage control with millivolt resolution, programmable jitter injection, and various eye margining features critical for AC characterization and conformance testing. Furthermore, the system integrates device power supplies with precise power sequencing and ramping controls, providing a comprehensive solution for both AC characterization and memory functional stress testing on any GDDR7 device.
Introspects M5512 has been designed in close collaboration with JEDEC members working on the GDDR7 specification, so it promises to meet all of their requirements for compliance testing. Notably, however, the device does not eliminate need for interoperability tests and still requires companies to develop their own test algorithms, but it's still a significant tool for bootstrapping device development and getting it to the point where chips can begin interop testing.
“In its quest to support the industry on GDDR7 deployment, Introspect Technology has worked tirelessly in the last few years with JEDEC members to develop the M5512 GDDR7 Memory Test System,” said Dr. Mohamed Hafed, CEO at Introspect Technology.
Nowadays highest-capacity hard drives are typically aimed at cloud service providers (CSPs) and enterprises, but this does not mean that creative professionals or regular users do not need them. To cater to demands of more regular consumers, Western Digital has started shipments of its Red Pro 24 TB HDDs, which are aimed at high-end NAS use for creative professionals with significant storage requirements.
Western Digital's Red Pro 24 TB hard drives come approximately 20 months after their 22 TB model hit retail in 2022, offering an incremental improvement to WD's highest-capacity NAS and consumer hard drive offering. The platform uses conventional magnetic recording (CMR), feature a 7200 RPM rotating speed, are equipped with a 512 MB cache, and use OptiNAND technology to improve reliability as well as optimize performance and power consumption. The HDDs are rated for an up to 287 MB/s media to cache transfer rate, which makes them some of the fastest hard drives around (albeit, still a bit slower compared to CSP and enterprise-oriented HDDs).
Just like other high-end network-attached storage-aimed HDDs, the Red Pro 24 TB hard drives use helium-filled platforms that are very similar to those designed for enterprise drives. Consequently, the Red Pro 24 TB HDD are equipped with rotation vibration sensors to anticipate and proactively counteract disturbances caused by increased vibration and multi-axis shock sensors to detect subtle shock events and automatically offset them with dynamic fly height technology to ensure that heads to not scratch disks.
UPDATE 4/2/2024: Western Digital has notified us that WD Red Pro fully support ArmorCache capability, even though it is not listed in datasheets.
What these drives lack compared Apparently, just like WD Gold and Ultraster 22 TB and 24 TB drives for enterprises and cloud datacenters, WD Red Pro HDDs fully support the ArmorCache feature that provides protection against power loss when write-cache is enabled (WCE mode) and enhances performance when write-cache is disabled (WCD mode).
On the reliability side of matters, Western Digital's Red Pro 24 TB HDDs are designed for 24/7 operation in vibrating environments, such as enterprise-grade NAS with loads of bays, and are rated for up to 550 TB/year workloads as well as up to 600,000 load/unload cycles, which is in line with what Western Digital's WD Gold and Ultrastar hard drives offer.
As for power consumption, the WD Red Pro 24 TB consumes up to 6.4W during read and write operations, up to 3.9W in idle mode, and up to 1.2W in standby/sleep mode.
Western Digital's Red Pro 24 TB (WD240KFGX) HDDs are now shipping to resellers as well as NAS makers, and are slated to be available shortly. Expect these hard drives to be slightly cheaper than the WD Gold 24 TB model.
Typical CPU coolers do the job for standard heat management but often fall short when it comes to quiet operation and peak cooling effectiveness. This gap pushes enthusiasts and PC builders towards specialized aftermarket solutions designed for their unique demands. The premium aftermarket cooling niche is fiercely competitive, with brands vying to offer top-notch thermal management solutions.
Today we're shining a light on DeepCool's AK620 Digital cooler, a notable entry in the high-end CPU cooler arena. At first blush, the AK620 Digital stands out from the crowd mostly for its integrated LCD screen. Yet aesthetics aside, underneath the snappy screen is a tower cooler that was first and foremost engineered to exceed the cooling needs of the most powerful mainstream CPUs. And it's a big cooler at that: with a weight of 1.5Kg and 162mm tall, this is no lightweight heatsink and fan assembly. All of which helps to set it apart in a competitive marketplace.
Offering some rare insight into the scale of HBM memory sales – and on its growth in the face of unprecedented demand from AI accelerator vendors – the company recently disclosed that it expects HBM sales to make up "a double-digit percentage of its DRAM chip sales" this year. Which if it comes to pass, would represent a significant jump in sales for the high-bandwidth, high-priced memory.
As first reported by Reuters, SK hynix CEO Kwak Noh-Jung has commented that he expects HBM sales will constitute a double-digit percentage of its DRAM chip sales in 2024. This prediction corroborate with estimates from TrendForce, who believe that, industry-wide, HBM will account for 20.1% of DRAM revenue in 2024, more than doubling HBM's 8.4% revenue share in 2023.
And while SK hynix does not break down its DRAM revenue by memory type on a regular basis, a bit of extrapolation indicates that they're on track to take in billions in HBM revenue for 2024 – having likely already crossed the billion dollar mark itself in 2023. Last year, SK hynix's DRAM revenue $15.941 billion, according to Statista and TrendForce. So SK hynix only needs 12.5% of its 2024 revenues to come from HBM (assuming flat or positive revenue overall) in order to pass 2 billion in HBM sales. And even this is a low-ball estimate.
Overall, SK hynix currently commands about 50% of HBM market, having largely split the market with Samsung over the last couple of years. Given that share, and that DRAM industry revenue is expected to increase to $84.150 billion in 2024, SK hynix could earn as much as $8.45 billion on HBM in 2024 if TrendForce's estimates prove accurate.
It should be noted that with demand for AI servers at record levels, all three leading makers of DRAM are poised to increase their HBM production capacity this year. Most notable here is a nearly-absent Micron, who was the first vendor to start shipping HBM3E memory to NVIDIA earlier this year. So SK hynix's near-majority of the HBM market may falter some this year, though with a growing pie they'll have little reason to complain. Ultimately, if sales of HBM reach $16.9 billion as projected, then all memory makers will be enjoying significant HBM revenue growth in the coming months.
Sources: Reuters, TrendForce
Now that JEDEC has published specification of GDDR7 memory, memory manufacturers are beginning to announce their initial products. The first out of the gate for this generation is Samsung, which has has quietly added its GDDR7 products to its official product catalog.
For now, Samsung lists two GDDR7 devices on its website: 16 Gbit chips rated for an up to 28 GT/s data transfer rate and a faster version running at up to 32 GT/s data transfer rate (which is in line with initial parts that Samsung announced in mid-2023). The chips feature a 512M x32 organization and come in a 266-pin FBGA packaging. The chips are already sampling, so Samsung's customers – GPU vendors, AI inference vendors, network product vendors, and the like – should already have GDDR7 chips in their labs.
The GDDR7 specification promises the maximum per-chip capacity of 64 Gbit (8 GB) and data transfer rates of 48 GT/s. Meanwhile, first generation GDDR7 chips (as announced so far) will feature a rather moderate capacity of 16 Gbit (2 GB) and a data transfer rate of up to 32 GT/s.
Performance-wise, the first generation of GDDR7 should provide a significant improvement in memory bandwidth over GDDR6 and GDDR6X. However capacity/density improvements will not come until memory manufacturers move to their next generation EUV-based process nodes. As a result, the first GDDR7-based graphics cards are unlikely to sport any memory capacity improvements. Though looking a bit farther down the road, Samsung and SK Hynix have previously told Tom's Hardware that they intend to reach mass production of 24 Gbit GDDR7 chips in 2025.
Otherwise, it is noteworthy that SK Hynix also demonstrated its GDDR7 chips at NVIDIA's GTC last week. So Samsung's competition should be close behind in delivering samples, and eventually mass production memory.
Source: Samsung (via @harukaze5719)
SK hynix is considering whether to build an advanced packaging facility in Indiana, reports the Wall Street Journal. If the company proceeds with the plan, it intends to invest $4 billion in it and construct one of the world's largest advanced packaging facilities. But to accomplish the project, SK hynix expects it will need help from the U.S. government.
Acknowledging the report but stopping short of confirming the company's plans, a company spokeswoman told the WSJ that SK hynix "is reviewing its advanced chip packaging investment in the U.S., but hasn’t made a final decision yet."
Companies like TSMC and Intel spend billions on advanced packaging facilities, but so far, no company has announced a chip packaging plant worth quite as much as SH hynix's $4 billion. The field of advanced packaging – CoWoS, passive silicon interposers, redistribution layers, die-to-die bonding, and other cutting edge technologies – has seen an explosion in demand in the last half-decade. As bandwidth advances with traditional organic packaging are largely played out, chip designers have needed to turn to more complex (and difficult to assemble) technologies in order to wire up an ever larger number of signals at ever-higher transfer rates. Which has turned advanced packaging into a bottleneck for high-end chip and accelerator production, driving a need for additional packaging facilities.
If SK hynix approves the project, the advanced packaging facility is expected to begin operations in 2028 and could create as many as 1,000 jobs. With an estimated cost of $4 billion, the plant is poised to become one of the largest advanced packaging facilities in the world.
Meanwhile, government backing is thought to be essential for investments of this scale, with potential state and federal tax incentives, according to the report. These incentives form part of a broader initiative to bolster the U.S. semiconductor industry and decrease dependence on memory produced in South Korea.
SK hynix is the world's leading producer of HBM memory, and is one of the key HBM suppliers to NVIDIA. Next generations of HBM memory (including HBM4 and HBM4E) will require even closer collaboration between chip designers, chipmakers, and memory makers. Therefore, packaging HBM in America could be a significant benefit for NVIDIA, AMD, and other U.S. chipmakers.
Investing in the Indiana facility will be a strategic move by SK hynix to enhance its advanced chip packaging capabilities in general and demonstrating dedication to the U.S. semiconductor industry.
Today, Intel announced that it is looking to progress its AI PC Acceleration program further by offering various new toolkits and devkits designed for software and hardware AI developers under a new AI PC Developer Program sub-initiative. Originally launched on October 23, the AI PC Acceleration program was created to connect hardware vendors with software developers, using Intel's vast resources and experience to develop a broader ecosystem as the world pivots to one driven by AI development.
Intel aims to maximize the potential of AI applications and software and broaden the whole AI-focused PC ecosystem by aiming for AI within 100 million Intel-driven AI PCs by 2025. The AI PC Developer Program aims to simplify the adoption of new AI technologies and frameworks on a larger scale. It provides access to various tools, workflows, AI-deployment frameworks, and developer kits, allowing developers to take advantage of the latest NPU found within Intel's Meteor Lake Core Ultra series of processors.
It also offers centralized resources like toolkits, documentation, and training to allow developers to fully utilize their software and hardware in tandem with the technologies associated with Meteor Lake (and beyond) to enhance AI and machine learning application performance. Such toolkits are already broadly used by developers, including Intel's open-source OpenVino.
Furthermore, this centralized resource platform is designed to streamline the AI development process, making it more efficient and effective for developers to integrate AI capabilities into their applications. It is designed to play a crucial role in Intel’s strategy to not only advance AI technology but also to make it more user-friendly and adaptable to various real-world applications.
Notably, this is both a software and a hardware play. Intel isn't just looking to court more software developers to utilize their AI resources, but they also want to get independent hardware vendors (IHVs) on board. OEMs and system assemblers are largely already covered under Microsoft's requirements for Windows certification, but Intel wants to get the individual parts vendors involved as well. How can AI be used to improve audio performance? Display performance? Storage performance? That's something that Intel wants to find out.
"We have made great strides with our AI PC Acceleration Program by working with the ecosystem. Today, with the addition of the AI PC Developer Program, we are expanding our reach to go beyond large ISVs and engage with small and medium sized players and aspiring developers" said Carla Rodriguez, Vice President and General Manager of Client Software Ecosystem Enabling. "Our goal is to drive a frictionless experience by offering a broad set of tools including the new AI-ready Developer Kit,"
The Intel AI PC Acceleration Program offers 24/7 access to resources and early reference hardware so that both ISVs and software developers can create and optimize workloads before launching retail components. Developers can join the AI PC Acceleration Program at their official webpage or email AIPCIHV@intel.com for further information
China has initiated a policy shift to eliminate American processors from government computers and servers, reports Financial Times. The decision is aimed to gradually eliminate processors from AMD and Intel from system used by China's government agencies, which will mean lower sales for U.S.-based chipmakers and higher sales of China's own CPUs.
The new procurement guidelines, introduced quietly at the end of 2023, mandates government entities to prioritize 'safe and reliable' processors and operating systems in their purchases. This directive is part of a concerted effort to bolster domestic technology and parallels a similar push within state-owned enterprises to embrace technology designed in China.
The list of approved processors and operating systems, published by China's Information Technology Security Evaluation Center, exclusively features Chinese companies. There are 18 approved processors that use a mix of architectures, including x86 and ARM, while the operating systems are based on open-source Linux software. Notably, the list includes chips from Huawei and Phytium, both of which are on the U.S. export blacklist.
This shift towards domestic technology is a cornerstone of China's national strategy for technological autonomy in the military, government, and state sectors. The guidelines provide clear and detailed instructions for exclusively using Chinese processors, marking a significant step in China's quest for self-reliance in technology.
State-owned enterprises have been instructed to complete their transition to domestic CPUs by 2027. Meanwhile, Chinese government entites have to submit progress reports on their IT system overhauls quarterly. Although some foreign technology will still be permitted, the emphasis is clearly on adopting local alternatives.
The move away from foreign hardware is expected to have a measurable impact on American tech companies. China is a major market for AMD (accounting for 15% of sales last year) and Intel (commanding 27% of Intel's revenue), contributing to a substantial portion of their sales. Additionally, Microsoft, while not disclosing specific figures, has acknowledged that China accounts for a small percentage of its revenues. And while government sales are only a fraction of overall China sales (as compared to the larger commercial PC business) the Chinese government is by no means a small customer.
Analysts questioned by Financial Times predict that the transition to domestic processors will advance more swiftly for server processors than for client PCs, due to the less complex software ecosystem needing replacement. They estimate that China will need to invest approximately $91 billion from 2023 to 2027 to overhaul the IT infrastructure in government and adjascent industries.
DeepCool is one of the few veterans in the PC power & cooling components field still active today. The Chinese company was first founded in 1996 and initially produced only coolers and cooling accessories, but quickly diversified into the PC Case and power supply unit (PSU) markets. To this day, DeepCool stays almost entirely focused on PC power & cooling products, with input devices and mousepads being their latest diversification attempt.
Today's review turns the spotlight toward DeepCool’s PSUs and, more specifically, the PX850G 850W ATX 3.0 PSU, which currently is their most popular power supply. The PX850G is engineered to balance all-around performance with reliability and cost, all while providing ATX 3.0 compliance. It is based on a highly popular high-output platform but, strangely, DeepCool rated the PX850G for operation up to 40°C.
When a major industry slowdown occurs, big companies tend to slowdown their mid-term and long-term capacity related investments. This is exactly what happened to SK hynix's Yongin Semiconductor Cluster, a major project announced in April 2021 and valued at $106 billion. While development of the site has been largely completed, only 35% of the initial shell building has been constructed, according to the Korean Ministry of Trade, Industry, and Energy.
"Approximately 35% of Fab 1 has been completed so far and site renovation is in smooth progress," a statement by the Korean Ministry of Trade, Industry, and Energy reads. "By 2046, over KRW 120 trillion ($90 billion today, $106 billion in 2021) in investment will be poured to complete Fabs 1 through 4, and construction of Fab 1's production line will commence in March next year. Once completed, the infrastructure will rank as the world's largest three-story fab."
The new semiconductor fabrication cluster by SK hynix announced almost exactly three years ago is primarily meant to be used to make DRAM for PCs, mobile devices, and servers using advanced extreme ultraviolet lithography (EUV) process technologies. The cluster, located near Yongin, South Korea, is intended to consist of four large fabs situated on a 4.15 million m2 site. With a planned capacity of approximately 800,000 wafer starts per month (WSPMs), it is set to be one of the world's largest semiconductor production hubs.
With that said, SK hynix's construction progress has been slower than the company first projected. The first fab in the complex was originally meant to come online in 2025, with construction starting in the fourth quarter of 2021. However, SK hynix began to cut its capital expenditures in the second half of 2022, and the Yongin Semiconductor Cluster project fell a victim of that cut. To be sure, the site continues to be developed, just at a slower pace; which is why some 35% of the first fab shell has been built at this point.
If completed as planned in 2021, the first phase of SK hynix Yongin operations would have been a major memory production facility costing $25 billion, equipped with EUV tools, and capable of 200,000-WSPM, according to reports from 2021.
Sources: Korean Ministry of Trade, Industry, and Energy; ComputerBase
Micron this week announced that it had begun sampling of its 256 GB multiplexer combined (MCR) DIMMs, the company's highest-capacity memory modules to date. These brand-new DDR5-based MCRDIMMs are aimed at next-generation servers, particularly those powered by Intel's Xeon Scalable 'Granite Rapids' processors that are set to support 12 or 24 memory slots per socket. Usage of these modules can enable datacenter machines with 3 TB or 6 TB of memory, with the combined ranks allowing for effect data rates of DDR5-8800.
"We also started sampling our 256 GB MCRDIMM module, which further enhances performance and increases DRAM content per server," said Sanjay Mehrotra, chief executive of Micron, in prepared remarks for the company's earnings call this week.
In addition to announcing sampling of these modules, Micron also demonstrated them at NVIDIA's GTC conference, where server vendors and customers alike are abuzz at building new servers for the next generation of AI accelerators. Our colleagues from Tom's Hardware have managed to grab a couple of pictures of Micron's 256 GB DDR5-8800 MCR DIMMs.
Image Credit: Tom's Hardware
Apparently, Micron's 256 GB DDR5-8800 MCRDIMMs come in two variants: a taller module with 80 DRAM chips distributed on both sides, and a standard-height module using 2Hi stacked packages. Both are based on monolithic 32 Gb DDR5 ICs and are engineered to cater to different server configurations with the standard-height MCRDIMM adressing 1U servers.The taller version consumes about 20W of power, which is in line with expectations as a 128 GB DDR5-8000 RDIMM consumes around 10W in DDR5-4800 mode. I have no idea about power consumption of the version that uses 2Hi packages, though expect it to be a little bit hotter and harder to cool down.
Image Credit: Tom's Hardware
Multiplexer Combined Ranks (MCR) DIMMs are dual-rank memory modules featuring a specialized buffer that allows both ranks to operate simultaneously. This buffer enables the two physical ranks to operate as though they were separate modules working in parallel, which allows for concurrent retrieval of 128 bytes of data from both ranks per clock cycle (compared to 64 bytes per cycle when it comes to regular memory modules), effectively doubling performance of a single module. Of course, since the modules retains physical interface of standard DDR5 modules (i.e., 72-bits), the buffer works with host at a very high data transfer rate to transfer that fetched data to the host CPU. These speeds exceed the standard DDR5 specifications, reaching 8800 MT/s in this case.
While MCR DIMMs make memory modules slightly more complex than regular RDIMMs, they increase performance and capacity of memory subsystem without increasing the number of memory modules involved, which makes it easier to build server motherboards. These modules are poised to play a crucial role in enabling the next generation of servers to handle increasingly demanding applications, particularly in the AI field.
Sources: Tom's Hardware, Micron
Being the first company to ship HBM3E memory has its perks for Micron, as the company has revealed that is has managed to sell out the entire supply of its advanced high-bandwidth memory for 2024, while most of their 2025 production has been allocated, as well. Micron's HBM3E memory (or how Micron alternatively calls it, HBM3 Gen2) was one of the first to be qualified for NVIDIA's updated H200/GH200 accelerators, so it looks like the DRAM maker will be a key supplier to the green company.
"Our HBM is sold out for calendar 2024, and the overwhelming majority of our 2025 supply has already been allocated," said Sanjay Mehrotra, chief executive of Micron, in prepared remarks for the company's earnings call this week. "We continue to expect HBM bit share equivalent to our overall DRAM bit share sometime in calendar 2025."
Micron's first HBM3E product is an 8-Hi 24 GB stack with a 1024-bit interface, 9.2 GT/s data transfer rate, and a total bandwidth of 1.2 TB/s. NVIDIA's H200 accelerator for artificial intelligence and high-performance computing will use six of these cubes, providing a total of 141 GB of accessible high-bandwidth memory.
"We are on track to generate several hundred million dollars of revenue from HBM in fiscal 2024 and expect HBM revenues to be accretive to our DRAM and overall gross margins starting in the fiscal third quarter," said Mehrotra.
The company has also began sampling its 12-Hi 36 GB stacks that offer a 50% more capacity. These KGSDs will ramp in 2025 and will be used for next generations of AI products. Meanwhile, it does not look like NVIDIA's B100 and B200 are going to use 36 GB HBM3E stacks, at least initially.
Demand for artificial intelligence servers set records last year, and it looks like it is going to remain high this year as well. Some analysts believe that NVIDIA's A100 and H100 processors (as well as their various derivatives) commanded as much as 80% of the entire AI processor market in 2023. And while this year NVIDIA will face tougher competition from AMD, AWS, D-Matrix, Intel, Tenstorrent, and other companies on the inference front, it looks like NVIDIA's H200 will still be the processor of choice for AI training, especially for big players like Meta and Microsoft, who already run fleets consisting of hundreds of thousands of NVIDIA accelerators. With that in mind, being a primary supplier of HBM3E for NVIDIA's H200 is a big deal for Micron as it enables it to finally capture a sizeable chunk of the HBM market, which is currently dominated by SK Hynix and Samsung, and where Micron controlled only about 10% as of last year.
Meanwhile, since every DRAM device inside an HBM stack has a wide interface, it is physically bigger than regular DDR4 or DDR5 ICs. As a result, the ramp of HBM3E memory will affect bit supply of commodity DRAMs from Micron, the company said.
"The ramp of HBM production will constrain supply growth in non-HBM products," Mehrotra said. "Industrywide, HBM3E consumes approximately three times the wafer supply as DDR5 to produce a given number of bits in the same technology node."
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