Connexion
Intel's Programmable Solutions Group (PSG) is broadening its FPGA product range with the introduction of six new programmable platforms aimed at different types of customers and workloads. In addition to a new sub-family of Agilex 5-series offerings, Intel is launching its all-new Agilex 3 series offerings along with new Agilex.
The highlight of today's announcement is the Intel Agilex 3 FPGA series of power and cost-optimized FPGAs in compact form factors. The family includes the Agilex 3 B-series FPGAs that boast a higher I/O density in compact form factors (compared to Intel Max 10 FPGAs) and are optimized for board and system management, including server platform management applications.
On the other side of the Agilex 3 spectrum is the C-series FPGAs that are engineered to provide supplementary capabilities, making them apt for a broad spectrum of complex programmable logic devices (CPLD) and FPGA applications across various industries. Intel says that its Agilex 3-series FPGAs will be available soon without disclosing when exactly.
Another noteworthy introduction is the Intel Agilex 5 FPGA E-series based on the 2nd Generation Hyperflex FPGA architecture and tailored for embedded edge applications and therefore featuring high performance efficiency. Intel produces these FPGAs in house using its Intel 7 manufacturing technology (formerly known as 10 nm Enhanced SuperFin), which is why it says that these parts deliver 1.6 times higher performance per watt compared to competing FPGAs made on a 16 nm-class process technology (possibly referring to Xilinx's FPGAs built in this process node). Additionally, this FPGA series integrates an AI tensor block, a feature previously exclusive to Intel's premium programmable parts, positioning it as a solution for edge AI tasks. Intel will start sampling Agilex 5 E-series parts with design software in Q1 2024. A system simulator for these FPGAs will be available in the cloud in late 2024.
Intel also said that it had begun shipments of its Intel Agilex 7 FPGAs with the R-Tile chiplet. These FPGAs offer a PCIe 5.0 interface with the CXL protocol on top that allow to quickly deploy programmable accelerators for specific tasks that can benefit from higher bandwidth and lower latencies.
In addition to revealing new FPGAs, Intel also said that the first commercial product based on its F2000X infrastructure processing unit platform is now shipping. The part is the Napatech F2070X IPU that has two 100 GbE ports and is powered by the Agilex AGFC023 FPGA and an Intel Xeon D SoC.
Rounding off the new introductions is the Nios V/c compact microcontroller, which is a soft-core IP, based on the RISC-V architecture, which can be programmed using the company's Quartus Prime Pro software.
The USB-IF and VESA released the specifications of USB4 v2 and DisplayPort 2.1 in Q4 2022. At that time, Intel also announced that their next-gen Thunderbolt specifications would build upon these standards. However, concrete details were not divulged. Today, the company is unveiling Thunderbolt 5 officially with discrete controllers in tow for both hosts and peripherals.
The USB4 v2 specifications have been public for almost a year now. As a result, the capabilities of Thunderbolt 5 on the technical front are not much of a secret. In fact, Intel had detailed most of them last year.
The technical aspects described above include:
A few additional details were provided as part of today's announcement. These are in addition to Thunderbolt 4 features.
Thunderbolt 5 also supports up to 240W power delivery (USB-PD EPR specifications). This is useful for gaming notebooks and other power-hungry systems connecting to a Thunderbolt 5 dock (and relying on it as a power source). However, this is an optional feature and is likely to be relegated to premium Thunderbolt 5 peripherals. The compulsory features related to the increase in available bandwidth translate to support for high-refresh rate high-resolution monitors, and support for external SSDs and eGFX with PCIe Gen4 x4 links.
Intel is bringing Thunderbolt 5 to the market with discrete silicon first. The Barlow Ridge family includes controllers for both hosts and accessories. Silicon meant for accessories are equipped with one upstream and three downstream Thunderbolt 5 ports. For computers, the controller takes in a DisplayPort 2.1 input along with a PCIe Gen4 x4 link to interface with the host.
The technical aspects of Barlow Ridge such as package size and TDP will be made public in the coming months. Intel expects Thunderbolt 5-equipped computers and accessories to launch in 2024. Technical collateral and other developer resources will become available in Q4 2023.
Based on the Thunderbolt 5 details presented today, it is clear that Thunderbolt ports will continue to remain the Type-C port that does it all. We would have liked some of the optional features (such as USB3 20G support) to become compulsory, but the other exciting updates in Thunderbolt 5 may make it easy for consumers to look past that. In any case, we have seen recent USB4 / Thunderbolt 4 implementations supporting that standard, so it is likely that at least some Thunderbolt 5 host ports will also support that standard.
Continuing their recent spending spree in expanding their foundry capabilities, Intel this morning has announced that it has struck a deal to acquire specialty foundry Tower Semiconductor for $5.4 billion. If approved by shareholders and regulatory authorities, the deal would result in Intel significantly expanding its own contract foundry capabilities, acquiring not only Tower’s various fabs and specialty production lines, but also the company’s experience in operating contract foundries over the long run.
The proposed deal marks the latest venture from Intel that is designed to bolster Intel Foundry Services’ (IFS) production capabilities. In the last month and a half alone, Intel has announced plans to build a $20B fab complex in Ohio that will, in part, be used to fab chips for IFS, as well as a $1B fund to support companies building new and critical technologies for the overall foundry ecosystem. The Tower Semiconductor acquisition, in turn, is yet another piece of the puzzle for IFS, fleshing out Intel’s foundry capabilities for more exotic products.
As a specialty foundry, the Israel-based Tower Semiconductor is best known for its analog offerings, as well as its other specialized process lines. Among the chip types produced by Tower are MEMS, RF CMOS, BiCMOS, CMOS image sensors, silicon–germanium transistors, and power management chips. Essentially, Tower makes most of the exotic chip types that logic-focused Intel does not – so much so that Intel has been a Tower customer long before today’s deal was announced. All of which is why Intel wants the firm and its capabilities: to boost IFS’s ability to make chips for customers who aren’t after a straight ASIC processor.
The proposed acquisition would also see Intel pick up ownership of/access to the 8 foundry facilities that Tower uses. This includes the Tower-owned 150mm and 200mm fabs in Israel and two 200mm fabs in the US. Meanwhile Tower also has majority ownership in two 200mm fabs and a 300mm fab in Japan, and a future 300mm facility in Italy that will be shared with ST Microelectronics. As is typical for analog and other specialty processes where density is not a critical factor (if not a detriment), all of these fabs are based around mature process nodes, ranging from 1000nm down to 65nm, which sits in stark contrast to Intel’s leading-edge logic fabs.
Along with Tower’s manufacturing technology, the proposed deal would also see Intel pick up Tower’s expertise in the contract foundry business, which is something the historically insular Intel lacks. On top of their fab services, Tower also offers its customers electronic design automation and design services using a range of IP, all of which will be folded into IFS’s expanded offerings as part of the deal. Consequently, although the company has already brought on executives and other personnel with contract fab experience in past hirings, this would be the single largest talent transaction for IFS.
All told, Intel currently expects the deal to take around 12 months to close, with the company paying $5.4 billion in cash from its balance sheet for Tower Semiconductor shares. Though approved by both the Intel and Tower Semiconductor boards, Tower’s stockholders will still need to approve the deal. Intel will also need regulatory approval from multiple governments in order to close the deal, to which the company isn’t expecting much objection to given the complementary nature of the two companies’ foundry offerings. Still, as the last week alone has proven, regulatory approval for multi-billion dollar acquisitions is not always guaranteed.
At the close of play today, Intel is announcing two major changes at the top of its organization. The big one is that EVP and GM of Intel’s Client Computing Group, Gregory Bryant, who led the company in their CES messaging only last week, is moving on to new ventures. After his 30-year stint at Intel, he is to be replaced by 25-year veteran Michelle Johnston Holthaus, currently EVP and Intel’s Chief Revenue Officer in charge of Communications, Sales, and Marketing. There’s also a new CFO coming in from Micron.
It’s a big surprise, seeing Gregory Bryant leave Intel. He has been leading the consumer platform team for a number of years, since June 2017, covering the last few generations of CPU and mobile launches through Intel’s tough times with bringing 10nm to revenue. He has overseen the launch of the Intel Evo initiative, and comes from an engineering background, although preferred to let other senior engineers talk to their strengths. Greg will leave Intel at the end of the month, for a new opportunity. It's actually quite a strange announcement, given that he led Intel's presentations at CES only last week - a time when he must've known that one foot was out the door. Analysts are reporting that his goals involve becoming a CEO somewhere, and that the opportunity he is leaving for is a big one. It also reduces the number of Bryants at senior levels of Intel down from three to one (Diane Bryant left in 2017).
Bryant’s replacement is Intel EVP and Chief Revenue Officer Michelle Johnston Holthaus. She is another Intel lifer, having spent 25 years at the company, joining in 1996. She has held multiple roles in reseller management, HQ central marketing and operations, global account management, and currently sits as GM of the Sales, Marketing, and Communications group. In recent memory Holthaus was the keynote speaker at Intel’s Partner Summit. Bringing her to the role is likely a move to strengthen Intel’s bonds with its OEM partners, an aspect that is seeing increased competition in traditional client OEM markets. It also means that Intel has two women leading its largest business units – Holthaus for Client Computing, and Sandra Rivera for Datacenter.
During the transition, Intel will be searching for a new leader of Intel’s sales, marketing, and communications group.
Also announced today is that Intel is to get a new Chief Financial Officer. It was already announced that current CFO, George Davis, was to retire in 2022 and the search was on for a replacement. That replacement has been found in the form of David Zinsner, who comes from his role as CFO at Micron. This position is effective January 17th, which is shortly before Intel’s end-of-year financial results on January 26th. George Davis is to remain at Intel in an advisory role until May to ensure a seamless transition. It’s key to point out that Intel’s search for a new CFO has been thought to aim to find an individual who has the same CAPEX expenditure aspirations as CEO Pat Gelsinger.
Lateo.net - Flux RSS en pagaille (pour en ajouter : @ moi) 